Reset Sequence Manager (Rsm); Introduction; Table 8. St7 Clock Sources - STMicroelectronics ST72361 Auto Series Manual

ST72361xx-Auto
output distortion and start-up stabilization time. The loading capacitance values must be
adjusted according to the selected oscillator.
These oscillators are not stopped during the RESET phase to avoid losing time in the
oscillator start-up phase.
Table 8.
5.5

Reset sequence manager (RSM)

5.5.1

Introduction

The reset sequence manager includes three RESET sources as shown in
● External RESET source pulse
●
Internal LVD reset (Low Voltage Detection)
● Internal watchdog reset
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of three phases as shown in
● Active phase depending on the reset source
●
256 or 4096 CPU clock cycle delay (selected by option byte)
● RESET vector fetch
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
ST7 clock sources
Doc ID 12468 Rev 3
Supply, reset and clock management
Hardware configuration
ST7
OSC1 OSC2
EXTERNAL
SOURCE
ST7
OSC1 OSC2
C C
L1
LOAD
CAPACITORS
L2
Figure 13:
Figure 12:
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