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Renesas H8/300H Series Manuals
Manuals and User Guides for Renesas H8/300H Series. We have
8
Renesas H8/300H Series manuals available for free PDF download: Hardware Manual, User Manual, Manual
Renesas H8/300H Series Hardware Manual (905 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 8.58 MB
Table of Contents
Sample Program
7
Table of Contents
11
Section 1 Overview
25
Overview
25
Block Diagram
31
Pin Description
32
Pin Arrangement
32
Pin Assignments in each Mode
34
Pin Functions
39
Differences between H8/3048F and H8/3048F-ONE
44
Section 2 CPU
49
Overview
49
Features
49
Differences from H8/300 CPU
50
CPU Operating Modes
51
Address Space
52
Register Configuration
53
Overview
53
General Registers
54
Control Registers
55
Initial CPU Register Values
56
Data Formats
57
General Register Data Formats
57
Memory Data Formats
59
Instruction Set
60
Instruction Set Overview
60
Instructions and Addressing Modes
61
Tables of Instructions Classified by Function
62
Basic Instruction Formats
71
Notes on Use of Bit Manipulation Instructions
72
Addressing Modes and Effective Address Calculation
74
Addressing Modes
74
Effective Address Calculation
76
Processing States
80
Overview
80
Program Execution State
81
Exception-Handling State
81
Exception-Handling Sequences
83
Bus-Released State
84
Reset State
84
Power-Down State
84
Basic Operational Timing
85
Overview
85
On-Chip Memory Access Timing
85
On-Chip Supporting Module Access Timing
86
Access to External Address Space
87
Section 3 MCU Operating Modes
89
Overview
89
Operating Mode Selection
89
Register Configuration
90
Mode Control Register (MDCR)
90
System Control Register (SYSCR)
91
Operating Mode Descriptions
93
Mode 1
93
Mode 2
93
Mode 3
93
Mode 4
93
Mode 5
93
Mode 6
94
Mode 7
94
Pin Functions in each Operating Mode
94
Memory Map in each Operating Mode
95
Section 4 Exception Handling
105
Overview
105
Exception Handling Types and Priority
105
Exception Handling Operation
105
Exception Vector Table
106
Reset
108
Overview
108
Reset Sequence
108
Interrupts after Reset
111
Interrupts
112
Trap Instruction
113
Stack Status after Exception Handling
113
Notes on Stack Usage
114
Section 5 Interrupt Controller
115
Overview
115
Features
115
Block Diagram
116
Pin Configuration
117
Register Configuration
117
Register Descriptions
118
System Control Register (SYSCR)
118
Interrupt Priority Registers a and B (IPRA, IPRB)
119
IRQ Status Register (ISR)
126
IRQ Enable Register (IER)
127
IRQ Sense Control Register (ISCR)
128
Interrupt Sources
129
External Interrupts
129
Internal Interrupts
130
Interrupt Vector Table
130
Interrupt Operation
134
Interrupt Handling Process
134
Interrupt Sequence
139
Interrupt Response Time
140
Usage Notes
141
Contention between Interrupt and Interrupt-Disabling Instruction
141
Instructions that Inhibit Interrupts
142
Interrupts During EEPMOV Instruction Execution
142
Usage Notes on External Interrupts
142
Notes on Non-Maskable Interrupts (NMI)
144
Section 6 Bus Controller
147
Overview
147
Features
147
Block Diagram
148
Input/Output Pins
149
Register Configuration
150
Register Descriptions
150
Bus Width Control Register (ABWCR)
150
Access State Control Register (ASTCR)
151
Wait Control Register (WCR)
152
Wait State Controller Enable Register (WCER)
153
Bus Release Control Register (BRCR)
154
Chip Select Control Register (CSCR)
155
Operation
157
Area Division
157
Chip Select Signals
158
Data Bus
160
Bus Control Signal Timing
161
Wait Modes
169
Interconnections with Memory (Example)
175
Bus Arbiter Operation
177
Usage Notes
180
Connection to Dynamic RAM and Pseudo-Static RAM
180
Register Write Timing
180
BREQ Input Timing
182
Transition to Software Standby Mode
182
Section 7 Refresh Controller
183
Overview
183
Features
183
Block Diagram
184
Input/Output Pins
185
Register Configuration
185
Register Descriptions
186
Refresh Control Register (RFSHCR)
186
Refresh Timer Control/Status Register (RTMCSR)
189
Refresh Timer Counter (RTCNT)
190
Refresh Time Constant Register (RTCOR)
191
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Renesas H8/300H Series Hardware Manual (845 pages)
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.52 MB
Table of Contents
Table of Contents
15
Section 1 Overview
29
Overview
29
Block Diagram
34
Pin Description
35
Pin Arrangement
35
Pin Assignments in each Mode
36
Pin Functions
41
Section 2 CPU
47
Overview
47
Features
47
Differences from H8/300 CPU
48
CPU Operating Modes
49
Address Space
50
Register Configuration
51
Overview
51
General Registers
52
Control Registers
53
Initial CPU Register Values
54
Data Formats
55
General Register Data Formats
55
Memory Data Formats
57
Instruction Set
58
Instruction Set Overview
58
Instructions and Addressing Modes
59
Tables of Instructions Classified by Function
60
Basic Instruction Formats
70
Notes on Use of Bit Manipulation Instructions
71
Addressing Modes and Effective Address Calculation
72
Addressing Modes
72
Effective Address Calculation
75
Processing States
79
Overview
79
Program Execution State
80
Exception-Handling State
80
Exception-Handling Sequences
82
Bus-Released State
83
Reset State
83
Power-Down State
83
Basic Operational Timing
84
Overview
84
On-Chip Memory Access Timing
84
On-Chip Supporting Module Access Timing
85
Access to External Address Space
86
Section 3 MCU Operating Modes
87
Overview
87
Operating Mode Selection
87
Register Configuration
88
Mode Control Register (MDCR)
88
System Control Register (SYSCR)
89
Operating Mode Descriptions
91
Mode 1
91
Mode 2
91
Mode 3
91
Mode 4
91
Mode 5
91
Mode 6
92
Mode 7
92
Pin Functions in each Operating Mode
92
Memory Map in each Operating Mode
93
Section 4 Exception Handling
97
Overview
97
Exception Handling Types and Priority
97
Exception Handling Operation
97
Exception Sources and Vector Table
98
Reset
100
Overview
100
Reset Sequence
100
Interrupts after Reset
103
Interrupts
104
Trap Instruction
105
Stack Status after Exception Handling
105
Notes on Use of the Stack
106
Section 5 Interrupt Controller
107
Overview
107
Features
107
Block Diagram
108
Pin Configuration
109
Register Configuration
109
Register Descriptions
110
System Control Register (SYSCR)
110
Interrupt Priority Registers a and B (IPRA, IPRB)
111
IRQ Status Register (ISR)
117
IRQ Enable Register (IER)
118
IRQ Sense Control Register (ISCR)
119
Interrupt Sources
120
External Interrupts
120
Internal Interrupts
121
Interrupt Exception Vector Table
121
Interrupt Operation
125
Interrupt Handling Process
125
Interrupt Exception Handling Sequence
130
Interrupt Response Time
131
Usage Notes
132
Contention between Interrupt Generation and Disabling
132
Instructions that Inhibit Interrupts
133
Interrupts During EEPMOV Instruction Execution
133
Notes on Use of External Interrupts
133
Section 6 Bus Controller
137
Overview
137
Features
137
Block Diagram
138
Pin Configuration
139
Register Configuration
140
Register Descriptions
140
Bus Width Control Register (ABWCR)
140
Access State Control Register (ASTCR)
141
Wait Control Register (WCR)
142
Wait State Controller Enable Register (WCER)
143
Bus Release Control Register (BRCR)
144
Chip Select Control Register (CSCR)
146
Operation
147
Area Division
147
Chip Select Signals
149
Data Bus
150
Bus Control Signal Timing
151
Wait Modes
159
Interconnections with Memory (Example)
165
Bus Arbiter Operation
167
Usage Notes
170
Connection to Dynamic RAM and Pseudo-Static RAM
170
Register Write Timing
170
BREQ Input Timing
172
Transition to Software Standby Mode
172
Renesas H8/300H Series Hardware Manual (442 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.49 MB
Table of Contents
Table of Contents
11
Section 1 Overview
31
Features
31
Section 1 Overview
32
Figure 1.1 Internal Block Diagram of H8/36912 Group
33
Internal Block Diagram
33
Figure 1.2 Internal Block Diagram of H8/36902 Group
34
Pin Arrangement
35
Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)
35
Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)
36
Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B)
37
Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B)
38
Table 1.1 Pin Functions
39
Pin Functions
39
Section 2 CPU
41
Address Space and Memory Map
42
Figure 2.1 Memory Map (1)
42
Section 2 CPU
42
Figure 2.1 Memory Map (2)
43
Register Configuration
44
Figure 2.2 CPU Registers
44
Figure 2.3 Usage of General Registers
45
General Registers
45
Condition-Code Register (CCR)
46
Figure 2.4 Relationship between Stack Pointer and Stack Area
46
Program Counter (PC)
46
Data Formats
48
General Register Data Formats
48
Figure 2.5 General Register Data Formats (1)
48
Figure 2.5 General Register Data Formats (2)
49
Memory Data Formats
50
Figure 2.6 Memory Data Formats
50
Instruction Set
51
Table of Instructions Classified by Function
51
Table 2.1 Operation Notation
51
Table 2.2 Data Transfer Instructions
52
Table 2.3 Arithmetic Operations Instructions (1)
53
Table 2.3 Arithmetic Operations Instructions (2)
54
Table 2.4 Logic Operations Instructions
55
Table 2.5 Shift Instructions
55
Table 2.6 Bit Manipulation Instructions (1)
56
Table 2.6 Bit Manipulation Instructions (2)
57
Table 2.7 Branch Instructions
58
Table 2.8 System Control Instructions
59
Basic Instruction Formats
60
Table 2.9 Block Data Transfer Instructions
60
Figure 2.7 Instruction Formats
61
Addressing Modes and Effective Address Calculation
62
Addressing Modes
62
Table 2.10 Addressing Modes
62
Table 2.11 Absolute Address Access Ranges
64
Effective Address Calculation
65
Figure 2.8 Branch Address Specification in Memory Indirect Mode
65
Table 2.12 Effective Address Calculation (1)
65
Table 2.12 Effective Address Calculation (2)
66
Basic Bus Cycle
67
Access to On-Chip Memory (RAM, ROM)
67
Figure 2.9 On-Chip Memory Access Cycle
67
On-Chip Peripheral Modules
68
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
68
Figure 2.11 CPU Operation States
69
CPU States
69
Usage Notes
70
Notes on Data Access to Empty Areas
70
EEPMOV Instruction
70
Bit Manipulation Instruction
70
Figure 2.12 State Transitions
70
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
71
Table 3.1 Exception Sources and Vector Address
77
Section 3 Exception Handling
77
Exception Sources and Vector Address
77
Register Descriptions
79
Interrupt Edge Select Register 1 (IEGR1)
79
Interrupt Edge Select Register 2 (IEGR2)
80
Interrupt Enable Register 1 (IENR1)
80
Interrupt Enable Register 2 (IENR2)
81
Interrupt Flag Register 1 (IRR1)
82
Interrupt Flag Register 2 (IRR2)
83
Wakeup Interrupt Flag Register (IWPR)
83
Reset Exception Handling
84
Interrupt Exception Handling
85
External Interrupts
85
Internal Interrupts
86
Figure 3.1 Reset Sequence
86
Interrupt Handling Sequence
87
Figure 3.2 Stack Status after Exception Handling
88
Interrupt Response Time
89
Table 3.2 Interrupt Wait States
89
Figure 3.3 Interrupt Sequence
90
Usage Notes
91
Interrupts after Reset
91
Notes on Stack Area Use
91
Notes on Rewriting Port Mode Registers
91
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
91
Section 4 Address Break
93
Figure 4.1 Block Diagram of Address Break
93
Register Descriptions
94
Address Break Control Register (ABRKCR)
94
Address Break Status Register (ABRKSR)
96
Break Address Registers (BARH, BARL)
96
Break Data Registers (BDRH, BDRL)
96
Operation
97
Figure 4.2 Address Break Interrupt Operation Example (1)
97
Figure 4.2 Address Break Interrupt Operation Example (2)
98
Figure 5.1 Block Diagram of Clock Pulse Generators
99
Section 5 Clock Pulse Generators
99
Features
100
Register Descriptions
101
RC Control Register (RCCR)
101
RC Trimming Data Protect Register (RCTRMDPR)
102
RC Trimming Data Register (RCTRMDR)
103
Clock Control/Status Register (CKCSR)
104
System Clock Select Operation
105
Figure 5.2 State Transition of System Clock
105
Clock Control Operation
106
Figure 5.3 Flowchart of Clock Switching On-Chip Oscillator Clock to External Clock (1)
106
Figure 5.4 Flowchart of Clock Switching External Clock to On-Chip Oscillator Clock (2)
107
Clock Change Timing
108
Figure 5.5 Timing Chart of Switching On-Chip Oscillator Clock to External Clock
108
Figure 5.6 Timing Chart to Switch External Clock to On-Chip Oscillator Clock
109
Figure 5.7 Example of Trimming Flow for On-Chip Oscillator Frequency
110
Trimming of On-Chip Oscillator Frequency
110
Figure 5.8 Timing Chart of Trimming of On-Chip Oscillator Frequency
111
External Oscillators
112
Connecting Crystal Resonator
112
Figure 5.9 Example of Connection to Crystal Resonator
112
Figure 5.10 Equivalent Circuit of Crystal Resonator
112
Table 5.1 Crystal Resonator Parameters
112
Connecting Ceramic Resonator
113
External Clock Input Method
113
Prescaler
113
Prescaler S
113
Figure 5.11 Example of Connection to Ceramic Resonator
113
Figure 5.12 Example of External Clock Input
113
Usage Notes
114
Note on Resonators
114
Notes on Board Design
114
Figure 5.13 Example of Incorrect Board Design
114
Section 6 Power-Down Modes
115
Register Descriptions
115
System Control Register 1 (SYSCR1)
116
Table 6.1 Operating Frequency and Wait Time
117
System Control Register 2 (SYSCR2)
118
Module Standby Control Register 1 (MSTCR1)
119
Module Standby Control Register 2 (MSTCR2)
120
Mode Transitions and States of LSI
121
Figure 6.1 Mode Transition Diagram
121
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
122
Table 6.3 Internal State in each Operating Mode
122
Sleep Mode
123
Standby Mode
123
Subsleep Mode
124
Operating Frequency in Active Mode
124
Direct Transition
124
Module Standby Function
125
Section 7 ROM
127
Block Configuration
127
Figure 7.1 Flash Memory Block Configuration
128
Register Descriptions
129
Flash Memory Control Register 1 (FLMCR1)
129
Flash Memory Control Register 2 (FLMCR2)
130
Erase Block Register 1 (EBR1)
131
Flash Memory Enable Register (FENR)
131
Advertisement
Renesas H8/300H Series Hardware Manual (434 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.67 MB
Table of Contents
General Precautions on Handling of Product
6
Preface
8
Table of Contents
11
Section 1 Overview
31
Features
31
Section 1 Overview
32
Internal Block Diagram
33
Figure 1.1 Internal Block Diagram of H8/36094 Group of F-ZTAT TM
33
Pin Assignments
34
Figure 1.2 Pin Assignments of H8/36094 Group of F-ZTAT TM (FP-64K, FP-64A)
34
Figure 1.3 Pin Assignments of H8/36094 Group of F-ZTAT TM (FP-48F, FP-48B, TNP-48)
35
Overview
35
Pin Functions
36
Table 1.1 Pin Functions
36
Section 2 CPU
39
Address Space and Memory Map
40
Figure 2.1 Memory Map
40
Register Configuration
41
Figure 2.2 CPU Registers
41
Figure 2.3 Usage of General Registers
42
General Registers
42
Appendix
43
Condition-Code Register (CCR)
43
Figure 2.4 Relationship between Stack Pointer and Stack Area
43
Program Counter (PC)
43
Data Formats
45
General Register Data Formats
45
Figure 2.5 General Register Data Formats (1)
45
Figure 2.5 General Register Data Formats (2)
46
Memory Data Formats
47
Figure 2.6 Memory Data Formats
47
Instruction Set
48
Table of Instructions Classified by Function
48
Table 2.1 Operation Notation
48
Table 2.2 Data Transfer Instructions
49
Table 2.3 Arithmetic Operations Instructions (1)
50
Table 2.3 Arithmetic Operations Instructions (2)
51
Table 2.4 Logic Operations Instructions
52
Table 2.5 Shift Instructions
52
Table 2.6 Bit Manipulation Instructions (1)
53
Table 2.6 Bit Manipulation Instructions (2)
54
Table 2.7 Branch Instructions
55
Table 2.8 System Control Instructions
56
Basic Instruction Formats
57
Table 2.9 Block Data Transfer Instructions
57
Addressing Modes and Effective Address Calculation
58
Addressing Modes
58
Figure 2.7 Instruction Formats
58
Table 2.10 Addressing Modes
59
Table 2.11 Absolute Address Access Ranges
60
Figure 2.8 Branch Address Specification in Memory Indirect Mode
61
Effective Address Calculation
62
Table 2.12 Effective Address Calculation (1)
62
Table 2.12 Effective Address Calculation (2)
63
Basic Bus Cycle
64
Access to On-Chip Memory (RAM, ROM)
64
Figure 2.9 On-Chip Memory Access Cycle
64
On-Chip Peripheral Modules
65
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
65
CPU States
66
Figure 2.11 CPU Operation States
66
Usage Notes
67
Notes on Data Access to Empty Areas
67
EEPMOV Instruction
67
Bit Manipulation Instruction
67
Figure 2.12 State Transitions
67
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
68
Section 3 Exception Handling
73
Exception Sources and Vector Address
73
Table 3.1 Exception Sources and Vector Address
73
Register Descriptions
75
Interrupt Edge Select Register 1 (IEGR1)
75
Interrupt Edge Select Register 2 (IEGR2)
76
Interrupt Enable Register 1 (IENR1)
77
Interrupt Flag Register 1 (IRR1)
78
Wakeup Interrupt Flag Register (IWPR)
79
Reset Exception Handling
81
Interrupt Exception Handling
81
External Interrupts
81
Figure 3.1 Reset Sequence
82
Internal Interrupts
83
Interrupt Handling Sequence
83
Interrupt Response Time
84
Figure 3.2 Stack Status after Exception Handling
84
Table 3.2 Interrupt Wait States
84
Figure 3.3 Interrupt Sequence
85
Usage Notes
86
Interrupts after Reset
86
Notes on Stack Area Use
86
Notes on Rewriting Port Mode Registers
86
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
86
Section 4 Address Break
87
Register Descriptions
87
Figure 4.1 Block Diagram of Address Break
87
Address Break Control Register (ABRKCR)
88
Address Break Status Register (ABRKSR)
89
Table 4.1 Access and Data Bus Used
89
Break Address Registers (BARH, BARL)
90
Break Data Registers (BDRH, BDRL)
90
Operation
90
Figure 4.2 Address Break Interrupt Operation Example (1)
91
Figure 4.2 Address Break Interrupt Operation Example (2)
91
Section 5 Clock Pulse Generators
93
Figure 5.1 Block Diagram of Clock Pulse Generators
93
Features
94
Register Descriptions
94
RC Control Register (RCCR)
95
RC Trimming Data Protect Register (RCTRMDPR)
96
RC Trimming Data Register (RCTRMDR)
97
Clock Control/Status Register (CKCSR)
98
System Clock Select Operation
100
Figure 5.2 State Transition of System Clock
100
Clock Control Operation
101
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled
101
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1) (from On-Chip Oscillator Clock to External Clock)
102
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (from External Clock to On-Chip Oscillator Clock)
103
Clock Switching Timing
104
Figure 5.6 Timing Chart of Switching from On-Chip Oscillator Clock to External Clock
104
Figure 5.7 Timing Chart to Switch from External Clock to On-Chip Oscillator Clock
105
Figure 5.8 External Oscillation Backup Timing
106
Trimming of On-Chip Oscillator Frequency
107
Figure 5.9 Example of Trimming Flow for On-Chip Oscillator Clock
107
Figure 5.10 Timing Chart of Trimming of On-Chip Oscillator Frequency
108
External Clock Oscillators
109
Connecting Crystal Resonator
109
Figure 5.11 Example of Connection to Crystal Resonator
109
Figure 5.12 Equivalent Circuit of Crystal Resonator
109
Table 5.1 Crystal Resonator Parameters
109
Connecting Ceramic Resonator
110
Inputting External Clock
110
Figure 5.13 Example of Connection to Ceramic Resonator
110
Figure 5.14 Example of External Clock Input
110
Subclock Oscillator
111
Connecting 32.768-Khz Crystal Resonator
111
Figure 5.15 Block Diagram of Subclock Oscillator
111
Figure 5.16 Typical Connection to 32.768-Khz Crystal Resonator
111
Figure 5.17 Equivalent Circuit of 32.768-Khz Crystal Resonator
111
Pin Connection When Not Using Subclock
112
Prescaler
112
Prescaler S
112
Prescaler W
112
Figure 5.18 Pin Connection When Not Using Subclock
112
Usage Notes
113
Note on Resonators
113
Notes on Board Design
113
Figure 5.19 Example of Incorrect Board Design
113
Section 6 Power-Down Modes
115
Register Descriptions
115
System Control Register 1 (SYSCR1)
115
System Control Register 2 (SYSCR2)
117
Table 6.1 Operating Frequency and Waiting Time
117
Module Standby Control Register 1 (MSTCR1)
118
Mode Transitions and States of LSI
119
Figure 6.1 Mode Transition Diagram
119
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
120
Table 6.3 Internal State in each Operating Mode
121
Sleep Mode
122
Standby Mode
122
Subactive Mode
123
Subsleep Mode
123
Operating Frequency in Active Mode
124
Direct Transition
124
Direct Transition from Active Mode to Subactive Mode
124
Direct Transition from Subactive Mode to Active Mode
125
Module Standby Function
125
Renesas H8/300H Series User Manual (408 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.85 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Appendix
24
Section 1 Overview
29
Features
29
Internal Block Diagram
31
Figure 1.1 Internal Block Diagram of H8/36912 Group
31
Figure 1.2 Internal Block Diagram of H8/36902 Group
32
Section 2 CPU
32
Section 2 CPU
31
Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32)
33
Pin Arrangement
33
Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32)
34
Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32)
35
Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32)
36
Table 1.1 Pin Functions
37
Pin Functions
37
Manual
38
Section 2 CPU
39
Address Space and Memory Map
40
Figure 2.1 Memory Map (1)
40
Figure 2.1 Memory Map (2)
41
Register Configuration
42
Figure 2.2 CPU Registers
42
Figure 2.3 Usage of General Registers
43
General Registers
43
Condition-Code Register (CCR)
44
Figure 2.4 Relationship between Stack Pointer and Stack Area
44
Program Counter (PC)
44
Data Formats
46
General Register Data Formats
46
Figure 2.5 General Register Data Formats (1)
46
Figure 2.5 General Register Data Formats (2)
47
Memory Data Formats
48
Figure 2.6 Memory Data Formats
48
Instruction Set
49
Table of Instructions Classified by Function
49
Table 2.1 Operation Notation
49
Table 2.2 Data Transfer Instructions
50
Table 2.3 Arithmetic Operations Instructions (1)
51
Table 2.3 Arithmetic Operations Instructions (2)
52
Table 2.4 Logic Operations Instructions
52
Table 2.5 Shift Instructions
53
Table 2.6 Bit Manipulation Instructions (1)
55
Table 2.6 Bit Manipulation Instructions (2)
55
Table 2.7 Branch Instructions
56
Table 2.8 System Control Instructions
57
Table 2.9 Block Data Transfer Instructions
57
Basic Instruction Formats
58
Figure 2.7 Instruction Formats
58
Addressing Modes and Effective Address Calculation
59
Addressing Modes
59
Table 2.10 Addressing Modes
59
Table 2.11 Absolute Address Access Ranges
60
Figure 2.8 Branch Address Specification in Memory Indirect Mode
61
Effective Address Calculation
62
Table 2.12 Effective Address Calculation (1)
62
Table 2.12 Effective Address Calculation (2)
63
Basic Bus Cycle
64
Access to On-Chip Memory (RAM, ROM)
64
Figure 2.9 On-Chip Memory Access Cycle
64
On-Chip Peripheral Modules
65
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
65
Figure 2.11 CPU Operation States
66
Figure 2.12 State Transitions
66
CPU States
66
Usage Notes
67
Notes on Data Access to Empty Areas
67
EEPMOV Instruction
67
Bit Manipulation Instruction
67
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same
68
Section 3 Exception Handling
73
Exception Sources and Vector Address
73
Register Descriptions
75
Interrupt Edge Select Register 1 (IEGR1)
75
Interrupt Edge Select Register 2 (IEGR2)
76
Interrupt Enable Register 1 (IENR1)
76
Interrupt Enable Register 2 (IENR2)
77
Interrupt Flag Register 1 (IRR1)
78
Interrupt Flag Register 2 (IRR2)
79
Wakeup Interrupt Flag Register (IWPR)
79
Reset Exception Handling
80
Interrupt Exception Handling
81
External Interrupts
81
Internal Interrupts
82
Interrupt Handling Sequence
82
Figure 3.1 Reset Sequence
82
Figure 3.2 Stack Status after Exception Handling
83
Interrupt Response Time
84
Table 3.2 Interrupt Wait States
84
Figure 3.3 Interrupt Sequence
85
Usage Notes
86
Interrupts after Reset
86
Notes on Stack Area Use
86
Notes on Rewriting Port Mode Registers
86
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
86
Section 4 Address Break
87
Register Descriptions
87
Figure 4.1 Block Diagram of Address Break
87
Address Break Control Register (ABRKCR)
88
Address Break Status Register (ABRKSR)
89
Table 4.1 Access and Data Bus Used
89
Break Address Registers (BARH, BARL)
90
Break Data Registers (BDRH, BDRL)
90
Operation
91
Figure 4.2 Address Break Interrupt Operation Example (1)
91
Figure 4.2 Address Break Interrupt Operation Example (2)
92
Section 5 Clock Pulse Generators
93
Figure 5.1 Block Diagram of Clock Pulse Generators
93
Features
94
Register Descriptions
95
RC Control Register (RCCR)
95
RC Trimming Data Protect Register (RCTRMDPR)
96
RC Trimming Data Register (RCTRMDR)
97
Clock Control/Status Register (CKCSR)
97
System Clock Select Operation
99
Figure 5.2 State Transition of System Clock
99
Clock Control Operation
100
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled
100
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1) (from Internal RC Clock to External Clock)
101
Figure 5.5 Flowchart of Clock Switching with Backup Function Disabled (2) (from External Clock to Internal RC Clock)
102
Clock Change Timing
103
Figure 5.6 Timing Chart of Switching Internal RC Clock to External Clock
103
Figure 5.7 Timing Chart to Switch External Clock to Internal RC Clock
104
Figure 5.8 External Oscillation Backup Timing
105
Figure 5.9 Example of Trimming Flow for Internal RC Oscillator Frequency
106
Trimming of Internal RC Oscillator Frequency
106
Figure 5.10 Timing Chart of Trimming of Internal RC Oscillator Frequency
107
External Oscillators
108
Connecting Crystal Resonator
108
Figure 5.11 Example of Connection to Crystal Resonator
108
Figure 5.12 Equivalent Circuit of Crystal Resonator
108
Table 5.1 Crystal Resonator Parameters
108
Connecting Ceramic Resonator
109
External Clock Input Method
109
Prescaler
109
Prescaler S
109
Figure 5.13 Example of Connection to Ceramic Resonator
109
Figure 5.14 Example of External Clock Input
109
Usage Notes
110
Note on Resonators
110
Notes on Board Design
110
Figure 5.15 Example of Incorrect Board Design
110
Section 6 Power-Down Modes
111
Register Descriptions
112
System Control Register 1 (SYSCR1)
112
System Control Register 2 (SYSCR2)
114
Module Standby Control Register 1 (MSTCR1)
115
Module Standby Control Register 2 (MSTCR2)
116
Mode Transitions and States of LSI
117
Figure 6.1 Mode Transition Diagram
117
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
117
Sleep Mode
118
Table 6.3 Internal State in each Operating Mode
118
Standby Mode
119
Subsleep Mode
119
Operating Frequency in Active Mode
120
Direct Transition
120
Module Standby Function
120
Section 7 ROM
121
Block Configuration
122
Figure 7.1 Flash Memory Block Configuration
123
Renesas H8/300H Series User Manual (272 pages)
Microcomputer Development Environment System
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.25 MB
Table of Contents
Table of Contents
15
Emulator Debugger Part
21
Section 1 Overview
23
Features
23
Warnings
24
Environmental Conditions
25
Emulator External Dimensions and Mass
25
Section 2 Preparation before Use
27
Emulator Preparation
27
Installing Emulator's Software
27
Connecting to the User System
28
Example of Connecting the User System Interface Cable Head to the User System
28
Plugging the User System Interface Cable Body into the Emulator
29
Plugging the User System Interface Cable Body into the Cable Head
29
Power Supply
30
AC Adapter
30
Polarity
30
Power Supply Monitor Circuit
30
SIMM Memory Module
30
Optional SIMM Memory Module Configuration
30
Hardware Interface
31
Signal Protection on the Emulator
31
User System Interface Circuits
31
Clock Oscillator
31
External Probe 1 (Ext1)/Trigger Output
31
External Probe 2 (Ext2)/Trigger Output
32
Voltage Follower Circuit
33
System Check
34
Communication Problems
39
Other Methods for Activating the Emulator
39
Uninstalling the Emulator's Software
39
Section 3 E6000 Emulator Functions
41
Debugging Features
41
Breakpoints
41
Trace
41
Execution Time Measurements
41
Performance Analysis
41
Bus Monitoring
42
Complex Event System (CES)
42
Event Channels
42
Range Channels
43
Breaks
43
Timing
43
Hardware Features
44
Memory
44
Clocks
45
Probes
45
Stack Trace Function
45
Online Help
45
Section 4 Preparation before Use
47
Renesas H8/300H Series Manual (95 pages)
Single Power Supply
Brand:
Renesas
| Category:
Computer Hardware
| Size: 1.43 MB
Table of Contents
General Precautions on Handling of Product
3
Preface
5
Table of Contents
9
Section 1 Overview
11
Introduction to F-ZTAT Microcomputers
11
On-Board Programming Modes
13
Boot Mode
13
User Program Mode
14
Manual
20
Section 2 F-ZTAT Microcomputer On-Board Programming Tool
23
Adapter Board
23
Overview of Adapter Board (HS0008EASF3H)
23
Adapter Board Structure
24
Adapter Board Operating Sequence
28
Opening and Closing Adapter Board Case
29
Setting the Power Selection Jumper
30
Connecting Adapter Board and User System
32
Control Signal Enable/Disable Switch and 1/0 Setting Switch
37
Connecting PC and Adapter Board
39
Turning the Adapter Board ON/OFF
40
On-Board Programming Software
41
Overview of On-Board Programming Software
41
On-Board Programming Software Transfer Process
43
On-Board Programming Software Write/Erase Control Program
52
Section 3 On-Board Programming
65
Installing the On-Board Programming Software
65
On-Board Programming Sequence (Boot Mode)
68
Writing in Boot Mode
69
On-Board Programming Sequence (User Program Mode)
78
Writing in User Program Mode
79
Section 4 Example Use of User System
89
Example Switching Circuit
89
Example SCI Switching Circuit
89
Example I/O Port Switching Circuit
91
Renesas H8/300H Series User Manual (34 pages)
User System Interface Cable
Brand:
Renesas
| Category:
Computer Hardware
| Size: 0.37 MB
Table of Contents
Important Information
7
Limited Warranty
8
Table of Contents
14
Section 1 Configuration
15
Section 2 Connection Procedures
17
Connecting User System Interface Cable to Emulator Station
17
Connecting User System Interface Cable to User System
19
Installing IC Socket
19
Soldering IC Socket
19
Inserting Cable Head
20
Fastening Cable Head
20
Fastening Cable Body
22
Recommended Dimensions for User System Mount Pad
23
Dimensions for User System Interface Cable Head
24
Resulting Dimensions after Connecting User System Interface Cable
25
Section 3 Installing the MCU to the User System
26
Section 4 Verifying Operation
28
Section 5 Notice
29
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