Renesas H8/300L Super Low Power Series Manuals

Manuals and User Guides for Renesas H8/300L Super Low Power Series. We have 3 Renesas H8/300L Super Low Power Series manuals available for free PDF download: Hardware Manual

Renesas H8/300L Super Low Power Series Hardware Manual (697 pages)

8-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 4 MB

Table of Contents
31
Section 1 Overview

43
- Overview
  43
- Internal Block Diagram
  49
- Pin Arrangement and Functions
  51
  - Pin Arrangement
    51
  - Pin Functions
    61
Section 2 CPU

67
- Overview
  67
  - Features
    67
  - Address Space
    68
  - Register Configuration
    68
- Register Descriptions
  69
  - General Registers
    69
  - Control Registers
    69
  - Initial Register Values
    71
- Data Formats
  71
  - Data Formats in General Registers
    72
  - Memory Data Formats
    73
- Addressing Modes
  74
  - Effective Address Calculation
    76
- Instruction Set
  80
  - Data Transfer Instructions
    82
  - Arithmetic Operations
    84
  - Logic Operations
    85
  - Shift Operations
    86
  - Bit Manipulations
    88
  - Branching Instructions
    92
  - System Control Instructions
    94
  - Block Data Transfer Instruction
    95
- Basic Operational Timing
  97
  - Access to On-Chip Memory (RAM, ROM)
    97
  - Access to On-Chip Peripheral Modules
    98
- CPU States
  99
  - Overview
    99
  - Program Execution State
    101
  - Program Halt State
    101
  - Exception-Handling State
    101
- Memory Map
  102
- Application Notes
  108
  - Notes on Data Access
    108
  - Notes on Bit Manipulation
    110
  - Notes on Use of the EEPMOV Instruction
    116
Section 3 Exception Handling

117
- Overview
  117
- Reset
  117
  - Reset Sequence
    117
  - Interrupt Immediately after Reset
    118
- Interrupts
  119
  - Overview
    119
  - Interrupt Control Registers
    121
  - External Interrupts
    132
  - Internal Interrupts
    133
  - Interrupt Operations
    134
  - Interrupt Response Time
    139
- Application Notes
  140
Section 4 Clock Pulse Generators

145
- Overview
  145
  - Block Diagram
    145
  - System Clock and Subclock
    146
  - Register Descriptions
    147
- System Clock Generator
  148
- Subclock Generator
  153
- Prescalers
  155
- Note on Oscillators
  156
- Notes on H8/38124 Group
  160
Section 5 Power-Down Modes

161
- Overview
  161
  - System Control Registers
    164
- Sleep Mode
  168
  - Transition to Sleep Mode
    168
  - Clearing Sleep Mode
    169
  - Clock Frequency in Sleep (Medium-Speed) Mode
    169
- Standby Mode
  170
- Watch Mode
  174
- Subsleep Mode
  176
  - Transition to Subsleep Mode
    176
  - Clearing Subsleep Mode
    176
- Subactive Mode
  177
  - Transition to Subactive Mode
    177
  - Clearing Subactive Mode
    177
  - Operating Frequency in Subactive Mode
    177
- Active (Medium-Speed) Mode
  178
- Direct Transfer
  179
- Module Standby Mode
  183
  - Setting Module Standby Mode
    183
  - Clearing Module Standby Mode
    183
Section 6 ROM

185
- Overview
  185
  - Block Diagram
    185
- H8/38024 PROM Mode
  186
  - Setting to PROM Mode
    186
  - Socket Adapter Pin Arrangement and Memory Map
    186
- H8/38024 Programming
  189
  - Writing and Verifying
    189
  - Programming Precautions
    194
- Reliability of Programmed Data
  195
- Flash Memory Overview
  196
  - Features
    196
  - Block Diagram
    197
  - Block Configuration
    198
  - Register Configuration
    200
- Descriptions of Registers of the Flash Memory
  200
- On-Board Programming Modes
  206
  - Boot Mode
    206
  - Programming/Erasing in User Program Mode
    209
  - Notes on On-Board Programming
    210
- Flash Memory Programming/Erasing
  210
- Program/Erase Protection
  216
  - Hardware Protection
    216
  - Software Protection
    216
  - Error Protection
    217
- Programmer Mode
  217
  - Socket Adapter
    217
  - Programmer Mode Commands
    218
  - Memory Read Mode
    221
  - Auto-Program Mode
    224
  - Auto-Erase Mode
    226
  - Status Read Mode
    227
  - Status Polling
    229
  - Programmer Mode Transition Time
    230
  - Notes on Memory Programming
    230
- Power-Down States for Flash Memory
  231
Section 7 RAM

233
- Overview
  233
  - Block Diagram
    233
Section 8 I/O Ports

235
- Overview
  235
- Port 1
  237
  - Overview
    237
  - Register Configuration and Description
    237
  - Pin Functions
    242
  - Pin States
    243
  - MOS Input Pull-Up
    243
- Port 3
  244
  - Overview
    244
  - Register Configuration and Description
    244
  - Pin Functions
    249
  - Pin States
    250
  - MOS Input Pull-Up
    250
- Port 4
  251
  - Overview
    251
  - Register Configuration and Description
    251
  - Pin Functions
    253
  - Pin States
    254
- Port 5
  255
  - Overview
    255
  - Register Configuration and Description
    255
  - Pin Functions
    258
  - Pin States
    259
  - MOS Input Pull-Up
    259
- Port 6
  260
  - Overview
    260
  - Register Configuration and Description
    260
  - Pin Functions
    262
  - Pin States
    263
  - MOS Input Pull-Up
    263
- Port 7
  264
  - Overview
    264
  - Register Configuration and Description
    264
  - Pin Functions
    266
  - Pin States
    266
- Port 8
  267
  - Overview
    267
  - Register Configuration and Description
    267
  - Pin Functions
    269
  - Pin States
    269
- Port 9
  270
  - Overview
    270
  - Register Configuration and Description
    271
  - Pin Functions
    274
  - Pin States
    274
- Port a
  275
  - Overview
    275
  - Register Configuration and Description
    275
  - Pin Functions
    277
  - Pin States
    278
- Port B
  279
  - Overview
    279
  - Register Configuration and Description
    279
  - Pin Functions
    281
- Input/Output Data Inversion Function
  282
- Application Note
  285
  - The Management of the Un-Use Terminal
    285
Section 9 Timers

287
- Overview
  287
- Timer a
  288
  - Overview
    288
  - Register Descriptions
    290
  - Timer Operation
    293
  - Timer a Operation States
    294
  - Application Note
    294
- Timer C
  295
  - Overview
    295
  - Register Descriptions
    297
  - Timer Operation
    300
  - Timer C Operation States
    302
- Timer F
  303
  - Overview
    303
  - Register Descriptions
    306
  - CPU Interface
    313
  - Operation
    316
  - Application Notes
    319
- Timer G
  323
  - Overview
    323
  - Register Descriptions
    325
  - Noise Canceler
    330
  - Operation
    332
  - Application Notes
    337
  - Timer G Application Example
    341
- Watchdog Timer
  342
  - Overview
    342
  - Register Descriptions
    345
  - Timer Operation
    351
  - Watchdog Timer Operation States
    352
- Asynchronous Event Counter (AEC)
  353
  - Overview
    353
  - Register Configurations
    356
  - Operation
    365
  - Asynchronous Event Counter Operation Modes
    370
  - Application Notes
    370
Section 10 Serial Communication Interface

373
- Overview
  373
  - Features
    373
  - Block Diagram
    375
  - Pin Configuration
    376
  - Register Configuration
    376
- Register Descriptions
  377
  - Receive Shift Register (RSR)
    377
  - Receive Data Register (RDR)
    377
  - Transmit Shift Register (TSR)
    378
  - Transmit Data Register (TDR)
    378
  - Serial Mode Register (SMR)
    379
  - Serial Control Register 3 (SCR3)
    382
  - Serial Status Register (SSR)
    386
  - Bit Rate Register (BRR)
    390
  - Clock Stop Register 1 (CKSTPR1)
    396
  - Serial Port Control Register (SPCR)
    396
- Operation
  398
  - Overview
    398
  - Operation in Asynchronous Mode
    402
  - Operation in Synchronous Mode
    411
  - Multiprocessor Communication Function
    418
- Interrupts
  425
- Application Notes
  426
Section 11 10-Bit PWM

431
- Overview
  431
  - Features
    431
  - Block Diagram
    432
  - Pin Configuration
    433
  - Register Configuration
    434
- Register Descriptions
  434
- Operation
  438
  - PWM Operation Modes
    439
Section 12 A/D Converter

441
- Overview
  441
  - Features
    441
  - Block Diagram
    442
  - Pin Configuration
    443
  - Register Configuration
    443
- Register Descriptions
  444
  - A/D Result Registers (ADRRH, ADRRL)
    444
  - A/D Mode Register (AMR)
    444
  - A/D Start Register (ADSR)
    446
  - Clock Stop Register 1 (CKSTPR1)
    447
- Operation
  448
- Interrupts
  449
- Typical Use
  449
- A/D Conversion Accuracy Definitions
  453
- Application Notes
  455
  - Permissible Signal Source Impedance
    455
  - Influences on Absolute Precision
    455
  - Additional Usage Notes
    456
Section 13 LCD Controller/Driver

457
- Overview
  457
  - Features
    457
  - Block Diagram
    458
  - Pin Configuration
    460
  - Register Configuration
    460
- Register Descriptions
  461
  - LCD Port Control Register (LPCR)
    461
  - LCD Control Register (LCR)
    463
  - LCD Control Register 2 (LCR2)
    465
  - Clock Stop Register 2 (CKSTPR2)
    467
- Operation
  468
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)

477
- Overview
  477
  - Features
    477
  - Block Diagram
    478
  - Pin Description
    479
  - Register Descriptions
    479
- Individual Register Descriptions
  479
- Operation
  485
  - Power-On Reset Circuit
    485
  - Low-Voltage Detection Circuit
    486

Renesas H8/300L Super Low Power Series Hardware Manual (562 pages)

8-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 3 MB

Table of Contents
17
Section 1 Overview

27
- Overview
  27
- Internal Block Diagram
  32
- Pin Arrangement and Functions
  34
  - Pin Arrangement
    34
  - Pin Functions
    46
Section 2 CPU

53
- Overview
  53
  - Features
    53
  - Address Space
    54
  - Register Configuration
    54
- Register Descriptions
  55
  - General Registers
    55
  - Control Registers
    55
  - Initial Register Values
    57
- Data Formats
  57
  - Data Formats in General Registers
    58
  - Memory Data Formats
    59
- Addressing Modes
  60
  - Effective Address Calculation
    62
- Instruction Set
  66
  - Data Transfer Instructions
    68
  - Arithmetic Operations
    70
  - Logic Operations
    71
  - Shift Operations
    71
  - Bit Manipulations
    73
  - Branching Instructions
    77
  - System Control Instructions
    79
  - Block Data Transfer Instruction
    80
- Basic Operational Timing
  81
  - Access to On-Chip Memory (RAM, ROM)
    81
  - Access to On-Chip Peripheral Modules
    82
- CPU States
  83
  - Overview
    83
  - Program Execution State
    85
  - Program Halt State
    85
  - Exception-Handling State
    85
- Memory Map
  86
- Application Notes
  88
Section 3 Exception Handling

97
- Overview
  97
- Reset
  97
  - Reset Sequence
    97
  - Interrupt Immediately after Reset
    98
- Interrupts
  99
  - Overview
    99
  - Interrupt Control Registers
    101
  - External Interrupts
    109
  - Internal Interrupts
    110
  - Interrupt Operations
    110
  - Interrupt Response Time
    115
- Application Notes
  115
  - Notes on Stack Area Use
    115
  - Notes on Rewriting Port Mode Registers
    116
Section 4 Clock Pulse Generators

119
- Overview
  119
  - Block Diagram
    119
  - System Clock and Subclock
    119
- System Clock Generator
  120
- Subclock Generator
  122
- Prescalers
  125
- Note on Oscillators
  126
Section 5 Power-Down Modes

127
- Overview
  127
  - System Control Registers
    130
- Sleep Mode
  133
  - Transition to Sleep Mode
    133
  - Clearing Sleep Mode
    133
- Standby Mode
  134
- Watch Mode
  137
- Subsleep Mode
  138
  - Transition to Subsleep Mode
    138
  - Clearing Subsleep Mode
    139
- Subactive Mode
  139
  - Transition to Subactive Mode
    139
  - Clearing Subactive Mode
    139
  - Operating Frequency in Subactive Mode
    140
- Active (Medium-Speed) Mode
  140
- Direct Transfer
  141
Section 6 ROM

145
- Overview
  145
  - Block Diagram
    145
- Overview of Flash Memory
  146
  - Features
    146
  - Block Diagram
    147
  - Flash Memory Operating Modes
    148
  - Pin Configuration
    151
  - Register Configuration
    152
- Flash Memory Register Descriptions
  152
- On-Board Programming Modes
  158
  - Boot Mode
    159
  - User Program Mode
    164
- Flash Memory Programming/Erasing
  166
  - Program Mode
    166
  - Program-Verify Mode
    167
  - Erase Mode
    169
  - Erase-Verify Mode
    169
- Flash Memory Protection
  171
  - Hardware Protection
    171
  - Software Protection
    172
  - Error Protection
    172
- Interrupt Handling During Flash Memory Programming and Erasing
  174
- Flash Memory Writer Mode
  175
  - Writer Mode Setting
    175
  - Socket Adapter and Memory Map
    175
  - Writer Mode Operation
    179
  - Memory Read Mode
    180
  - Auto-Program Mode
    184
  - Auto-Erase Mode
    186
  - Status Read Mode
    187
  - Status Polling
    188
  - Writer Mode Transition Time
    189
  - Notes on Memory Programming
    189
- Flash Memory Programming and Erasing Precautions
  190
- Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
  192
Section 7 RAM

193
- Overview
  193
  - Block Diagram
    193
Section 8 I/O Ports

195
- Overview
  195
- Port 1
  198
  - Overview
    198
  - Register Configuration and Description
    199
  - Pin Functions
    204
  - Pin States
    207
  - MOS Input Pull-Up
    208
- Port 2
  208
  - Overview
    208
  - Register Configuration and Description
    209
  - Pin Functions
    213
  - Pin States
    214
- Port 3 (H8/3857 Group Only)
  215
  - Overview
    215
  - Register Configuration and Description
    215
  - Pin Functions
    218
  - Pin States
    219
  - MOS Input Pull-Up
    219
- Port 4
  220
  - Overview
    220
  - Register Configuration and Description
    220
  - Pin Functions
    222
  - Pin States
    223
- Port 5
  223
  - Overview
    223
  - Register Configuration and Description
    224
  - Pin Functions
    226
  - Pin States
    226
  - MOS Input Pull-Up
    226
- Port 9 [Chip-Internal I/O Port]
  227
  - Overview
    227
  - Register Configuration and Description
    227
  - Pin Functions
    228
  - Pin States
    229
- Port a [Chip-Internal I/O Port]
  229
  - Overview
    229
  - Register Configuration and Description
    230
  - Pin Functions
    231
  - Pin States
    231
- Port B
  232
  - Overview
    232
  - Register Configuration and Description
    233
Section 9 Timers

235
- Overview
  235
- Timer a
  236
  - Overview
    236
  - Register Descriptions
    238
  - Timer Operation
    240
  - Timer a Operation States
    241
- Timer B
  241
  - Overview
    241
  - Register Descriptions
    243
  - Timer Operation
    245
  - Timer B Operation States
    246
- Timer C (H8/3857 Group Only)
  246
  - Overview
    246
  - Register Descriptions
    248
  - Timer Operation
    250
  - Timer C Operation States
    252
- Timer F
  252
  - Overview
    252
  - Register Descriptions
    255
  - Interface with the CPU
    261
  - Timer Operation
    264
  - Application Notes
    266
- Watchdog Timer [H8/3857F and H8/3854F Only]
  267
  - Overview
    267
  - Register Descriptions
    269
  - Operation
    272
  - Watchdog Timer Operating Modes
    273
Section 10 Serial Communication Interface

275
- Overview
  275
- SCI1 (H8/3857 Group Only)
  276
  - Overview
    276
  - Register Descriptions
    278
  - Operation
    282
  - Interrupts
    285
  - Application Notes
    285
- Sci3
  286
  - Overview
    286
  - Register Descriptions
    288
  - Operation
    305
  - Operation in Asynchronous Mode
    309
  - Operation in Synchronous Mode
    318
  - Multiprocessor Communication Function
    325
  - Interrupts
    331
  - Application Notes
    332
Section 11 14-Bit PWM (H8/3857 Group Only)

337
- Overview
  337
  - Features
    337
  - Block Diagram
    337
  - Pin Configuration
    338
  - Register Configuration
    338
- Register Descriptions
  338
  - PWM Control Register (PWCR)
    338
  - PWM Data Registers U and L (PWDRU, PWDRL)
    339
- Operation
  340
Section 12 A/D Converter

341
- Overview
  341
  - Features
    341
  - Block Diagram
    342
  - Pin Configuration
    343
  - Register Configuration
    343
- Register Descriptions
  344
  - A/D Result Register (ADRR)
    344
  - A/D Mode Register (AMR)
    344
  - A/D Start Register (ADSR)
    346
- Operation
  347
  - A/D Conversion Operation
    347
  - Start of A/D Conversion by External Trigger Input
    347
- Interrupts
  348
- Typical Use
  348
- Application Notes
  351
Section 13 Dot Matrix LCD Controller (H8/3857 Group)

353
- Overview
  353
  - Features
    353
  - Block Diagram
    354
  - Pin Configuration
    355
  - Register Configuration
    356
- Register Descriptions
  356
  - Index Register (IR)
    356
  - Control Register 1 (LR0)
    357
  - Control Register 2 (LR1)
    359
  - Address Register (LR2)
    361
  - Frame Frequency Setting Register (LR3)
    362
  - Display Data Register (LR4)
    364
  - Display Start Line Register (LR5)
    364
  - Blink Register (LR6)
    365
  - Blink Start Line Register (LR8)
    365
  - Blink End Line Register (LR9)
    366
  - Contrast Control Register (LRA)
    366
- Operation
  368
  - System Overview
    368
  - CPU Interface
    369
  - LCD Drive Pin Functions
    372
  - Display Memory Configuration and Display
    373
  - Display Data Output
    375
  - Register and Display Memory Access
    379
  - Scroll Function
    382
  - Blink Function
    384
  - Module Standby Mode
    386
  - 13.3.10 Power-On and Power-Off Procedures
    387
  - 13.3.11 Power Supply Circuit
    388
  - 13.3.12 LCD Drive Power Supply Voltages
    389
  - 13.3.13 LCD Voltage Generation Circuit
    391
  - 13.3.14 Contrast Control Circuit
    399
  - 13.3.15 LCD Drive Bias Selection Circuit
    400

Renesas H8/300L Super Low Power Series Hardware Manual (551 pages)

8-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 3 MB

Table of Contents
13
Section 1 Overview
23
Overview
23
Internal Block Diagram
28
Pin Arrangement and Functions
29
Pin Arrangement
29
Pin Functions
32
Section 2 CPU
37
Overview
37
Features
37
Address Space
38
Register Configuration
38
Register Descriptions
40
General Registers
40
Control Registers
40
Initial Register Values
42
Data Formats
42
Data Formats in General Registers
43
Memory Data Formats
44
Addressing Modes
45
Effective Address Calculation
47
Instruction Set
51
Data Transfer Instructions
53
Arithmetic Operations
55
Logic Operations
56
Shift Operations
56
Bit Manipulations
58
Branching Instructions
62
System Control Instructions
64
Block Data Transfer Instruction
65
Basic Operational Timing
66
Access to On-Chip Memory (RAM, ROM)
66
Access to On-Chip Peripheral Modules
67
CPU States
68
Overview
68
Program Execution State
70
Program Halt State
70
Exception-Handling State
70
Memory Map
71
Application Notes
72
Notes on Data Access
72
Notes on Bit Manipulation
74
Notes on Use of the EEPMOV Instruction
80
Section 3 Exception Handling
81
Overview
81
Reset
81
Reset Sequence
81
Interrupt Immediately after Reset
83
Interrupts
83
Overview
83
Interrupt Control Registers
85
External Interrupts
93
Internal Interrupts
94
Interrupt Operations
94
Interrupt Response Time
99
Application Notes
100
Notes on Stack Area Use
100
Notes on Rewriting Port Mode Registers
101
Section 4 Clock Pulse Generators
103
Overview
103
Block Diagram
103
System Clock and Subclock
103
System Clock Generator
104
Subclock Generator
106
Prescalers
107
Note on Oscillators
108
Section 5 Power-Down Modes
109
Overview
109
System Control Registers
112
Sleep Mode
116
Transition to Sleep Mode
116
Clearing Sleep Mode
116
Clock Frequency in Sleep (Medium-Speed) Mode
117
Standby Mode
117
Transition to Standby Mode
117
Clearing Standby Mode
117
Oscillator Settling Time after Standby Mode Is Cleared
118
Watch Mode
118
Transition to Watch Mode
118
Clearing Watch Mode
119
Oscillator Settling Time after Watch Mode Is Cleared
119
Subsleep Mode
119
Transition to Subsleep Mode
119
Clearing Subsleep Mode
120
Subactive Mode
120
Transition to Subactive Mode
120
Clearing Subactive Mode
120
Operating Frequency in Subactive Mode
121
Active (Medium-Speed) Mode
121
Transition to Active (Medium-Speed) Mode
121
Clearing Active (Medium-Speed) Mode
121
Operating Frequency in Active (Medium-Speed) Mode
121
Direct Transfer
122
Section 6 ROM
125
Overview
125
Block Diagram
125
PROM Mode
126
Setting to PROM Mode
126
Memory Map
126
Programming
127
Writing and Verifying
128
Programming Precautions
131
Reliability of Programmed Data
132
Flash Memory Overview
133
Principle of Flash Memory Operation
133
Mode Pin Settings and ROM Space
134
Features
134
Block Diagram
135
Pin Configuration
136
Register Configuration
136
Flash Memory Register Descriptions
137
Flash Memory Control Register (FLMCR)
137
Erase Block Register 1 (EBR1)
139
Erase Block Register 2 (EBR2)
140
On-Board Programming Modes
142
Boot Mode
142
User Program Mode
147
Programming and Erasing Flash Memory
149
Program Mode
149
Program-Verify Mode
150
Programming Flowchart and Sample Program
151
Erase Mode
154
Erase-Verify Mode
154
Erase Flowcharts and Sample Programs
155
Prewrite-Verify Mode
169
Protect Modes
170
Interrupt Handling During Flash Memory Programming/Erasing
171
Flash Memory PROM Mode (H8/3644F, H8/3643F, and H8/3642AF)
172
PROM Mode Setting
172
Memory Map
172
Operation in PROM Mode
173
Flash Memory Programming and Erasing Precautions
182
Section 7 RAM
189
Overview
189
Block Diagram
189
Section 8 I/O Ports
191
Overview
191
Port 1
193
Overview
193
Register Configuration and Description
193
Pin Functions
197
Pin States
198
MOS Input Pull-Up
198
Port 2
199
Overview
199
Register Configuration and Description
199
Pin Functions
201
Pin States
201
Port 3
202
Overview
202
Register Configuration and Description
202
Pin Functions
206
Pin States
207
MOS Input Pull-Up
207
Port 5
208
Overview
208
Register Configuration and Description
208
Pin Functions
210
Pin States
211
MOS Input Pull-Up
211
Port 6
212
Overview
212
Register Configuration and Description
212
Pin Functions
213
Pin States
214
Port 7
214
Overview
214
Register Configuration and Description
214
Pin Functions
216
Pin States
217
Port 8
217
Overview
217
Register Configuration and Description
218
Pin Functions
219
Pin States
220
Port 9
221
Overview
221
Register Configuration and Description
221
Pin Functions
222
Pin States
223
Port B
223
Overview
223
Register Configuration and Description
223
Pin Functions
224
Pin States
224
Section 9 Timers
225
Overview
225
Timer a
226
Overview
226
Register Descriptions
228
Timer Operation
230
Timer a Operation States
231
Timer B1
231
Overview
231
Register Descriptions
233
Timer Operation
235
Timer B1 Operation States
236
Timer V
237
Overview
237
Register Descriptions
240
Timer Operation
246
Timer V Operation Modes
251
Interrupt Sources
251
Application Examples
251
Application Notes
254
Timer X
260
Overview
260
Register Descriptions
264
CPU Interface
275
Timer Operation
278
Timer X Operation Modes
285
Interrupt Sources
285
Timer X Application Example
286
Application Notes
287
Watchdog Timer
292
Overview
292
Register Descriptions
293
Timer Operation
296
Watchdog Timer Operation States
297
Section 10 Serial Communication Interface
299
Overview
299
Sci1
299
Register Descriptions
301
Operation in Synchronous Mode
306
Operation in SSB Mode
309
Interrupts
311
Sci3
311
Overview
311
Register Descriptions
314
Operation
331
Operation in Asynchronous Mode
335
Operation in Synchronous Mode
344
Multiprocessor Communication Function
351
Interrupts
358
Application Notes
359
Section 11 14-Bit PWM
363
Overview
363
Features
363
Block Diagram
363
Pin Configuration
364
Register Configuration
364
Register Descriptions
364
PWM Control Register (PWCR)
364
PWM Data Registers U and L (PWDRU, PWDRL)
365
Operation
366
Section 12 A/D Converter
367
Overview
367
Features
367
Block Diagram
368
Pin Configuration
369
Register Configuration
369
Register Descriptions
370
A/D Result Register (ADRR)
370
A/D Mode Register (AMR)
370

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Renesas H8/300L Super Low Power Series Manuals

Renesas H8/300L Super Low Power Series Hardware Manual (697 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 10-Bit PWM

Section 12 A/D Converter

Section 13 LCD Controller/Driver

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)

Renesas H8/300L Super Low Power Series Hardware Manual (562 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 14-Bit PWM (H8/3857 Group Only)

Section 12 A/D Converter

Section 13 Dot Matrix LCD Controller (H8/3857 Group)

Renesas H8/300L Super Low Power Series Hardware Manual (551 pages)

Table of Contents

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