20. Usage Notes; Notes On Clock Generation Circuit; Stop Mode; Wait Mode - Renesas R8C Series User Manual

R8C/1A Group, R8C/1B Group

20. Usage Notes

20.1

Notes on Clock Generation Circuit

20.1.1

Stop Mode

When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
20.1.2

Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
20.1.3

Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used if the main clock frequency is below 2 MHz, set bits
OCD1 to OCD0 to 00b (oscillation stop detection function disabled) in this case.
20.1.4

Oscillation Circuit Constants

Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
20.1.5

High-Speed On-Chip Oscillator Clock

The high-speed on-chip oscillator frequency may be changed up to 10%
during auto-program operation or auto-erase operation.
The high-speed on-chip oscillator frequency after auto-program operation ends or auto-erase operation ends is
held the state before the program command or block erase command is generated. Also, this note is not
applicable when the read array command, read status register command, or clear status register command is
generated. The application products must be designed with careful considerations for the frequency change.
NOTE:
1.Change ratio to 8 MHz frequency adjusted in shipping.
Rev.1.30 Dec 08, 2006
REJ09B0252-0130
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001 :
NOP
NOP
NOP
NOP
BCLR
FSET
WAIT
NOP
NOP
NOP
NOP
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1,FMR0 ; CPU rewrite mode disabled
0,PRCR ; Protect disabled
I ; Enable interrupt
0,CM1 ; Stop mode
LABEL_001
1,FMR0 ; CPU rewrite mode disabled
I ; Enable interrupt
; Wait mode
(1)
20. Usage Notes
in flash memory CPU rewrite mode