Interrupt Enable Register (Fier) - Renesas H8S/2100 Series Hardware Manual

• FDLL
Bit Bit Name
7 to 0 Bit 7 to
bit 0
Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value)
16.3.6

Interrupt Enable Register (FIER)

FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR
is 0.
Bit Bit Name

7 to 4
3 EDSSI
2 ELSI
1 ETBEI
0 ERBFI
Initial Value R/W
All 0 R/W
Initial Value R/W
All 0 R
0 R/W
0 R/W
0 R/W
0 R/W
Section 16 Serial Communication Interface with FIFO (SCIF)
Description
Lower 8 bits of divisor latch
Description
Reserved
This bit is always read as 0 and cannot be modified.
Modem Status Interrupt Enable
0: Modem status interrupt disabled
1: Modem status interrupt enabled
Receive Line Status Interrupt Enable
0: Receive line status interrupt disabled
1: Receive line status interrupt enabled
FTHR Empty Interrupt Enable
0: FTHR empty interrupt disabled
1: FTHR empty interrupt enabled
Receive Data Ready Interrupt Enable
A character timeout interrupt is included when the
FIFO is enabled.
0: Receive data ready interrupt disabled
1: Receive data ready interrupt enabled
Rev. 1.00 May 09, 2008 Page 461 of 954
REJ09B0462-0100