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X
1/2
IN
P2
latch
0
P2
/S
0
CLK
SM3
P2
latch
1
P2
/S
1
OUT
SM3
P2
/S
2
IN
Note: When the data is set in the serial I/O register (address 00DD
the register functions as the serial I/O shift register.
Fig. 2.7.1 Serial I/O block diagram
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.7.2 Serial I/O mode register (address 00DC
1/2
Synchronous circuit
SM5 : LSB
Serial I/O shift register (8)
SM6
0
Serial I/O mode register (SM) [Address 00DC
B
Name
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
Synchronous clock
2
selection bit (SM2)
Serial I/O port
3
selection bit (SM3)
Fix this bit to "0."
4
Transfer direction
5
selection bit (SM5)
6
Serial input pin
selection bit (SM6)
Nothing is assigned. This bit is a write disable bit.
7
When this bit is read out, the value is "0."
7220 Group User's Manual
FUNCTIONAL DESCRIPTION
Frequency
divider
1/4
1/8
1/16
SM1
SM2
SM0
S
Clock source
generating circuit
Serial I/O counter (8)
MSB
(Address 00DD
)
16
8
),
16
Functions
b1 b0
0
0: f(X
)/4
IN
0
1: f(X
)/16
IN
1
0: f(X
)/32
IN
1
1: f(X
)/64
IN
0: External clock
1: Internal clock
0: P2
, P2
functions
0
1
as port
1: S
, S
CLK
OUT
0: LSB first
1: MSB first
0: Input signal from S
1: Input signal from S
)
16
2.7 Serial I/O
Data bus
Selection gate :
Connected to black
side at reset.
SM : Serial I/O mode register
Serial I/O interrupt
request
]
16
After reset R W
0
R W
0
R W
0
R W
0
R W
0
R W
pin
IN
0
R W
pin
OUT
0
R —
2-41
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