Serial Extension Mode Register (Scemr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.13

Serial Extension Mode Register (SCEMR)

The CPU can always read from or write to SCEMR. Setting the BGDM bit in this register to 1 allows the baud rate
generator in this module to operate in double-speed mode when asynchronous mode is selected (by setting the C/A bit in
SCSMR to 0) and an internal clock is selected as a clock source and the SCK pin is set as an input pin (by setting the
CKE[1:0] bits in SCSCR to 00).
The base clock frequency within a bit period in asynchronous mode can be switched by the setting of the ABCS bit.
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
—
15 to 8
7 BGDM
—
6 to 1
0 ABCS
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Baud Rate Generator Double-Speed Mode
When the BGDM bit is set to 1, the baud rate generator in this module operates
in double-speed mode. This bit is valid only when asynchronous mode is
selected by setting the C/A bit in SCSMR to 0 and an internal clock is selected
as a clock source and the SCK pin is set as an input pin by setting the CKE[1:0]
bits in SCSCR to 00. In other settings, use normal mode.
0: Normal mode
1: Double-speed mode
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Base Clock Select in Asynchronous Mode
This bit selects the base clock frequency within a bit period in asynchronous
mode. This bit is valid only in asynchronous mode (when the C/A bit in SCSMR
is 0).
0: Base clock frequency is 16 times the bit rate
1: Base clock frequency is 8 times the bit rate
14. Serial Communication Interface with FIFO
9 8 7 6 5
- - BGDM - -
0 0 0 0 0
R R R/W R R
4 3 2 1 0
- - - - ABCS
0 0 0 0 0
R R R R R/W
14-25