Clock-Asynchronous Serial I/O Mode (Compliant With The Sim Interface) - Renesas M16C Series User Manual

M30240 Group

1.2.23.3 Clock-asynchronous serial I/O mode (compliant with the SIM interface)

The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this func-
tion. Table 1.29 shows the specifications of clock-asynchronous serial I/O mode (compliant with the
SIM interface). Figure 1.92 shows the typical transmit/receive timing in UART mode.
Table 1.29: Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 0378
• One stop bit (bit 4 of address 0378
• With the direct format chosen
Transfer data
format
• With the inverse format chosen
• With the internal clock chosen (bit 3 of address 0378
Transfer clock
Transmission /
• Disable the CTS and RTS function (bit 4 of address 037C
reception control
• The sleep mode select function is not available for UART2
Other settings
• Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D
• To start transmission, the following requirements must be met:
Transmission start
condition
• To start reception, the following requirements must be met:
Reception start
condition
• When transmitting
Interrupt request
generation timing
• When receiving
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 3)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
Error detection
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: 'n' denotes the value 00
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Also, the UARTi receive interrupt request bit
is not set to "1".
Rev.1.00 Sep 24, 2003 Page 96 of 360
Set parity to "even" (bit 5 and bit 6 of address 0378
Set data logic to "direct" (bit 6 of address 037D
Set transfer format to LSB (bit 7 of address 037C
Set parity to "odd" (bit 5 and bit 6 of address 0378
Set data logic to "inverse" (bit 6 of address 037D
Set transfer format to MSB (bit 7 of address 037C
Transmit enable bit (bit 0 of address 037D
Transmit buffer empty flag (bit 1 of address 037D
Reception enable bit (bit 2 of address 037D
Detection of a start bit
When data transmission from the UART2 transfer register is completed (bit 4 of address 037D
When data transfer from the UART2 receive register to the UART2 receive buffer register is completed
On the reception side, an "L" level is output from the TxD2 pin by use of the parity error signal output
function (bit 7 of address 037D
On the transmission side, a parity error is detected by the level of input to the RxD2 pin when a
transmission interrupt occurs
to FF that is set to the UARTi bit rate generator.
16 16
Specification
= "0")
16
= "1" and "1" respectively)
16
= "0").
16
= "0").
16
= "0" and "1" respectively)
16
= "1")
16
= "1")
16
= "0"): fi / 16 (n + 1) (Note 1): fi=f1, f8, f32
16
= "1")
16
) = "1"
16
) = "0"
16
) = "1"
16
= "1") when a parity error is detected
16
UART0 to UART2
= "101 ")
16 2
= "1")
16
= "1")
16