Flash Memory Control Register 2 (Flmcr2); Erase Block Registers 1 And 2 (Ebr1, Ebr2) - Renesas H8S/2158 User Manual

24.5.2

Flash Memory Control Register 2 (FLMCR2)

FLMCR2 monitors the state of flash memory programming/erasing protection (error protection)
and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to
H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software
standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in
FLMCR1 is cleared to 0.
Bit Bit Name Initial Value
7 FLER 0
6 to 2 — All 0
1 ESU 0
0 PSU 0
24.5.3

Erase Block Registers 1 and 2 (EBR1, EBR2)

EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are
initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active
mode, or sub-sleep mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at
a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0.
R/W Description
R Indicates that an error has occurred during flash
memory programming/erasing. When this bit is set
to 1, flash memory goes to the error-protection state.
For details, see section 24.9.3, Error Protection.
R/(W) Reserved
The initial value should not be changed.
R/W Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it is
cleared to 0, the erase setup state is cancelled. Set
this bit to 1 before setting the E bit in FLMCR1 to 1.
R/W Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When it
is cleared to 0, the program setup state is cancelled.
Set this bit to 1 before setting the P bit in FLMCR1
to 1.
Rev. 3.00 Jan 25, 2006 page 725 of 872
Section 24 ROM
REJ09B0286-0300