Irq Enable Register (Ier); Irq Status Register (Isr); Keyboard Matrix Interrupt Mask Registers (Kmimra, Kmimr) Wake-Up Event Interrupt Mask Register (Wuemrb) - Renesas H8S/2111B Hardware Manual

5.3.5

IRQ Enable Register (IER)

IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit Bit Name
7 IRQ7E
6 IRQ6E
5 IRQ5E
4 IRQ4E
3 IRQ3E
2 IRQ2E
1 IRQ1E
0 IRQ0E
5.3.6

IRQ Status Register (ISR)

The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit Bit Name
7 IRQ7F
6 IRQ6F
5 IRQ5F
4 IRQ4F
3 IRQ3F
2 IRQ2F
1 IRQ1F
0 IRQ0F
Note: Only 0 can be written, for flag clearing.
*
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)
The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs
(KIN15 to KIN0), and wake-up event interrupt inputs (WUE7 to WUE0).
Initial
Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial
Value R/W
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
0
R/(W)*
Description
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this bit is
1.
Description
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
When reading IRQnF flag when IRQnF = 1, then
writing 0 to IRQnF flag
When interrupt exception handling is executed when
low-level detection is set and IRQn input is high
(n = 7 to 0)
When IRQn interrupt exception handling is executed
when falling-edge, rising-edge, or both-edge detection
is set
Rev. 1.00, 05/04, page 73 of 544