Irq Enable Register (Ier) - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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5.3.3

IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit
Bit Name
7
IRQ7E
6
IRQ6E
5
IRQ5E
4
IRQ4E
3
IRQ3E
2
IRQ2E
1
IRQ1E
0
IRQ0E
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
IRQ7 Enable
The IRQ7 interrupt request is enabled when this bit is
1
IRQ6 Enable
The IRQ6 interrupt request is enabled when this bit is
1
IRQ5 Enable
The IRQ5 interrupt request is enabled when this bit is
1
IRQ4 Enable
The IRQ4 interrupt request is enabled when this bit is
1
IRQ3 Enable
The IRQ3 interrupt request is enabled when this bit is
1
IRQ2 Enable
The IRQ2 interrupt request is enabled when this bit is
1
IRQ1 Enable
The IRQ1 interrupt request is enabled when this bit is
1
IRQ0 Enable
The IRQ0 interrupt request is enabled when this bit is
1
Rev. 1.00, 09/03, page 71 of 704

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