Irq Enable Register (Ier) - Renesas H8S/2368 Series Hardware Manual

Bit Bit Name
−
3
2 IPR2
1 IPR1
0 IPR0
5.3.3

IRQ Enable Register (IER)

IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit
Bit Name
−
15 to 8
7 IRQ7E
6 IRQ6E
5 IRQ5E
4 IRQ4E
3 IRQ3E
Rev. 2.00, 05/03, page 84 of 820
Initial Value R/W
−
0
1 R/W
1 R/W
1 R/W
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Reserved
This bit is always read as 0 and cannot be
modified.
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
Description
Reserved
The write value should always be 0.
IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.