Irq Enable Register (Ier) - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer
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Section 5 Interrupt Controller
5.3.4

IRQ Enable Register (IER)

IER enables or disables interrupt requests IRQ14 to IRQ0.
Bit
15
Bit Name
Initial Value
0
R/W
R/W
Bit
7
Bit Name
IRQ7E
Initial Value
0
R/W
R/W
Bit
Bit Name
15
14
IRQ14E
13
IRQ13E
12
IRQ12E
11
IRQ11E
10
IRQ10E
9
IRQ9E
Rev. 3.00 Mar. 14, 2006 Page 94 of 804
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14
13
IRQ14E
IRQ13E
IRQ12E
0
0
R/W
R/W
6
5
IRQ6E
IRQ5E
IRQ4E
0
0
R/W
R/W
Initial
Value
R/W
Description
0
R/W
Reserved
This bit is always read as 0. The write value should
always be 0.
0
R/W
IRQ14 Enable
The IRQ14 interrupt request is enabled when this bit
is 1.
0
R/W
IRQ13 Enable
The IRQ13 interrupt request is enabled when this bit
is 1.
0
R/W
IRQ12 Enable
The IRQ12 interrupt request is enabled when this bit
is 1.
0
R/W
IRQ11 Enable
The IRQ11 interrupt request is enabled when this bit
is 1.
0
R/W
IRQ10 Enable
The IRQ10 interrupt request is enabled when this bit
is 1.
0
R/W
IRQ9 Enable
The IRQ9 interrupt request is enabled when this bit is 1.
12
11
IRQ11E
IRQ10E
0
0
R/W
R/W
R/W
4
3
IRQ3E
IRQ2E
0
0
R/W
R/W
R/W
10
9
8
IRQ9E
IRQ8E
0
0
0
R/W
R/W
2
1
0
IRQ1E
IRQ0E
0
0
0
R/W
R/W

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