Read/Write Timing - Renesas NU85E Preliminary User's Manual

4.9.3 Read/write timing

(1) Read timing
Read data is output from the bus slave side in synchronization with the rising edge of the VBCLK signal
immediately after the end of address output to the bus slave. Following this, the bus master fetches (samples)
the data in synchronization with the next falling edge of the VBCLK signal.
However, if the VMAHLD signal has been input at an active level (high level), the bus slave outputs data in
synchronization with the rising edge of the VBCLK signal immediately after the active-level VMAHLD was input,
and the bus master fetches (samples) the data in synchronization with the next falling edge of the VBCLK signal.
(2) Write timing
Write data is output from the NU85E in synchronization with the falling edge of the VBCLK signal half clock after
the address is output to the bus slave.
The following pages show the read/write timing of the bus master and slaves connected to the VSB. The
diagrams show the timing seen from the NU85E side when the NU85E has bus access right.
Remark O mark: Sampling timing
A.x: Arbitrary address output from the VMA27 to VMA0 pins
D.x: I/O data for address "A.x"
: Arbitrary level (for input), or undefined status (for output)
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Preliminary User's Manual A14874EJ3V0UM