Read Strobe Timing Control Register (Rdncr); Figure 6.2 Read Strobe Negation Timing (Example Of 3-State Access Space) - Renesas H8S/2368 Series Hardware Manual

6.3.4

Read Strobe Timing Control Register (RDNCR)

RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit Bit Name
7 RDN7
6 RDN6
5 RDN5
4 RDN4
3 RDN3
2 RDN2
1 RDN1
0 RDN0
RDNn = 0
Data
RDNn = 1
Data

Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)

Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
T
1
Description
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is
negated one half-state earlier than that for an
area for which the RDNn bit is cleared to 0. The
read data setup and hold time specifications are
also one half-state earlier.
0: In an area n read access, the RD is negated
at the end of the read cycle
1: In an area n read access, the RD is negated
one half-state before the end of the read
cycle
Bus cycle
T
2
Rev. 2.00, 05/03, page 117 of 820
(n = 7 to 0)
T
3