Read Strobe Timing Control Register (Rdncr) - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.2.4

Read Strobe Timing Control Register (RDNCR)

RDNCR selects the negation timing of the read strobe signal (RD) when reading the external
address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.
Bit 15
Bit Name RDN7
Initial Value 0
R/W R/W
Bit 7

Bit Name
Initial Value 0
R/W R
Bit Bit Name
15 RDN7
14 RDN6
13 RDN5
12 RDN4
11 RDN3
10 RDN2
9 RDN1
8 RDN0

7 to 0
Notes: 1. In an external address space which is specified as byte control SRAM interface, the
RDNCR setting is ignored and the same operation when RDNn = 1 is performed.
2. In an external address space which is specified as burst ROM interface, the RDNCR
setting is ignored and the same operation when RDNn = 0 is performed.
Rev.2.00 Jun. 28, 2007 Page 132 of 666
REJ09B0311-0200
14 13
RDN6 RDN5
0 0
R/W R/W
6 5
 
0 0
R R
Initial
Value R/W Description
0 R/W Read Strobe Timing Control
0 R/W These bits set the negation timing of the read strobe in a
corresponding area read access.
0 R/W
As shown in figure 6.2, the read strobe for an area for
0 R/W
which the RDNn bit is set to 1 is negated one half-cycle
0 R/W
earlier than that for an area for which the RDNn bit is
cleared to 0. The read data setup and hold time are also
0 R/W
given one half-cycle earlier.
0 R/W
0: In an area n read access, the RD signal is negated at
0 R/W
1: In an area n read access, the RD signal is negated one
(n = 7 to 0)
All 0 R Reserved
These are read-only bits and cannot be modified.
12 11
RDN4 RDN3
0 0
R/W R/W
4 3
 
0 0
R R
the end of the read cycle
half-cycle before the end of the read cycle
10 9
RDN2 RDN1
0 0
R/W R/W
2 1
 
0 0
R R
8
RDN0
0
R/W
0

0
R