Stop 0 Mode; Table 50. Lpsleep - STMicroelectronics STM32WL5 Series Reference Manual

Power control (PWR)
The table below details how to exit the LPSleep mode.
LPSleep mode
Mode entry
Mode exit
Wake-up latency
6.5.7

Stop 0 mode

The Stop 0 mode is based on the CPU Deep-Sleep mode combined with the peripheral
clock gating. The voltage regulator is configured in main regulator mode. In Stop 0 mode, all
clocks in the V
disabled. Some peripherals with the wake-up capability (I2Cx (x = 1, 3), USARTx (x = 1, 2)
and LPUART1) can switch on HSI16 to receive a frame, and switch off HSI16 after receiving
the frame if it is not a wake-up frame. In this case, the HSI16 clock is propagated only to the
peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than V
The BOR and PDR can be activated to sample periodically the supply voltage. This option
enabled by setting the ULPEN bit of the PWR_CR3 register allows decreasing the current
consumption in this mode, but any drop of the voltage below the operating conditions
between two active periods of the supply detector results in a non-generation of PDR reset.
I/O states in Stop 0 mode
In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.
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Table 50. LPSleep

LPSleep mode is entered from the LPRun mode.
WFI (wait for interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex system control register.
LPSleep mode is entered from the LPRun mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex system control register.
If WFI or return from ISR was used for entry
Interrupt: refer to
table
If WFE was used for entry and SEVONPEND = 0:
Wake-up event: refer to
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to
and Table 90: CPU2 vector table
Wake-up event: refer to
After exiting the LPSleep mode, the MCU is in LPRun mode.
None
domain are stopped.PLL, MSI, HSI16 and HSE32 oscillators are
CORE
are used.
BOR0
RM0453 Rev 5
Description
Table 89: CPU1 vector table, and
Table 93: Wake-up interrupts
Table 93: Wake-up interrupts
RM0453
Table 90: CPU2 vector
Table 89: CPU1 vector table,