ST72361xx-Auto
23.2.2
16-bit and 8-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R or
OC2R register.
23.3
ROM devices only
23.3.1
16-bit timer PWM mode buffering feature change
In all devices, the frequency and period of the PWM signal are controlled by comparing the
counter with a 16-bit buffer updated by the OCiHR and OCiLR registers. In ROM devices,
contrary to the description in
not inhibited after a write instruction to the OCiHR register. Instead the buffer update at the
end of the PWM period is inhibited until OCiLR is written. This improved buffer handling is
fully compatible with applications written for Flash devices.
Pulse width modulation
Doc ID 12468 Rev 3
Important notes
mode, the output compare function is
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