Figure 39. Event Generation Of The Dma Request Line Multiplexer Channel - STMicroelectronics STM32WLEx Reference Manual

DMA request multiplexer (DMAMUX)

Figure 39. Event generation of the DMA request line multiplexer channel

dmamux_req_outx
DMA request counter
Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1
If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in
Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note: A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.
Synchronization overrun and interrupt
If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.
Note: The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA
controller. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CFRDMAMUX_CCFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.
390/1306
Selected
dmamux_reqx
3
SE
EGE
dmamux_evtx
Selected DMA request line transferred to the output
2 1 0 3 2
DMA request counter reaches zero
Event is generated on the output
DMA request counter auto-reloads with NBREQ value
Figure 38
RM0461 Rev 5
1 0 3 2 1
and Figure 39.
RM0461
DMA request pending
Not pending
0
MSv41975V1