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Section 29 List of Registers
29.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed. The number of
access states indicates the number of states based on the specified reference clock.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Name
EtherC mode register
EtherC status register
EtherC interrupt permission register
PHY interface register
MAC address high register
MAC address low register
Receive frame length register
PHY status register
Transmit retry over counter register
Delayed collision detect counter
register
Lost carrier counter register
Carrier not detect counter register
CRC error frame counter register
Frame receive error counter register
Too-short frame receive counter
register
Too-long frame receive counter
register
Residual-bit frame counter register
Multicast address frame counter
register
IPG register
Automatic PAUSE frame set register
Manual PAUSE frame set register
Rev. 1.00 Mar. 12, 2008 Page 1074 of 1178
REJ09B0403-0100
Number
Abbreviation
of Bits
ECMR
32
ECSR
32
ECSIPR
32
PIR
32
MAHR
32
MALR
32
RFLR
32
PSR
32
TROCR
32
CDCR
32
LCCR
32
CNDCR
32
CEFCR
32
FRECR
32
TSFRCR
32
TLFRCR
32
RFCR
32
MAFCR
32
IPGR
32
APR
32
MPR
32
Data
Bus
Address
Module
Width
H'F900
EtherC
16
H'F904
EtherC
16
H'F908
EtherC
16
H'F90C
EtherC
16
H'F910
EtherC
16
H'F914
EtherC
16
H'F918
EtherC
16
H'F91C
EtherC
16
H'F920
EtherC
16
H'F924
EtherC
16
H'F928
EtherC
16
H'F92C
EtherC
16
H'F934
EtherC
16
H'F938
EtherC
16
H'F93C
EtherC
16
H'F940
EtherC
16
H'F944
EtherC
16
H'F948
EtherC
16
H'F954
EtherC
16
H'F958
EtherC
16
H'F95C
EtherC
16
Number
of Access
States
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
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