Fifo Control Register (Scfcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.9

FIFO Control Register (SCFCR)

SCFCR resets the quantity of data in the transmit and receive FIFO data registers, sets the trigger data quantity, and
contains an enable bit for loop-back testing. SCFCR can always be read and written to by the CPU.
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
—
15 to 11
10 to 8 RSTRG[2:0]
7, 6 RTRG[1:0]
5, 4 TTRG[1:0]
3 MCE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - -
0 0 0 0 0
R R R R R/W
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
000 R/W RTS Output Active Trigger
When the quantity of receive data in receive FIFO data register (SCFRDR)
becomes equal to or greater than the trigger set number shown below, RTS
signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
00 R/W Receive FIFO Data Trigger
Set the quantity of receive data which sets the receive data full (RDF) flag in the
serial status register (SCFSR). The RDF flag is set to 1 when the quantity of
receive data stored in the receive FIFO data register (SCFRDR) becomes equal
to or greater than the set trigger number shown below.
•
Asynchronous mode
00: 1
01: 4
10: 8
11: 14
Note:
00 R/W Transmit FIFO Data Trigger
Set the quantity of remaining transmit data which sets the transmit FIFO data
register empty (TDFE) flag in the serial status register (SCFSR). The TDFE flag
is set to 1 when the quantity of transmit data in the transmit FIFO data register
(SCFTDR) becomes equal to or less than the set trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Values in parentheses mean the number of empty bytes in SCFTDR
0 R/W Modem Control Enable
Enables modem control signals CTS and RTS.
For channels 3 and 4 in clock synchronous mode, MCE bit should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the input value, and RTS is also
14. Serial Communication Interface with FIFO
9 8 7 6
RSTRG[2:0] RTRG[1:0]
0 0 0 0
R/W R/W R/W R/W R/W
In clock synchronous mode, to transfer the receive data using the
direct memory access controller, set the receive trigger number
to 1. If set to other than 1, CPU must read the receive data left in
SCFRDR.
when the TDFE flag is set to 1.
fixed at 0.
5 4 3 2 1
TTRG[1:0] MCE TFRST RFRST
0 0 0 0 0
R/W R/W R/W R/W
•
Clock synchronous mode
00: 1
01: 2
10: 8
11: 14
0
LOOP
0
R/W
14-19