Fifo Control Register (Ffcr) - Renesas H8S/2100 Series Hardware Manual

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.8

FIFO Control Register (FFCR)

FFCR is a write-only register that controls transmit/receive FIFOs.
Bit Bit Name
7 RCVRTRIG1
6 RCVRTRIG0
5, 4 –
3 DMAMODE
2 XMITFRST
1 RCVRFRST
0 FIFOE
Rev. 1.00 May 09, 2008 Page 464 of 954
REJ09B0462-0100
Initial Value R/W
0 W
0 W
 

0
0 W
0 W
0 W
Description
Receive FIFO Interrupt Trigger Level 1, 0
These bits set the trigger level of the receive FIFO
interrupt.
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes
Reserved
These bits cannot be modified.
DMA Mode
This bit is not supported and cannot be modified.
Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FRSR data is not cleared. This bit is
automatically cleared.
Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FTSR data is not cleared.
This bit is automatically cleared.
FIFO Enable
0: Transmit/receive FIFOs disabled
All bytes of these FIFOs are cleared.
1: Transmit/receive FIFOs enabled