Altera cyclone V Technical Reference page 2102

Hard processor system

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Host periodic TX FIFO buffer is empty (can be further programmed to

indicate half-empty).

Host channels interrupt received.

Incomplete periodic transfer is pending at the end of the microframe.

Host port status interrupt received.

External host initiated resume is detected.

Reset is detected when in suspend or normal mode.

USB suspend mode is detected.

Data fetch is suspended due to TX FIFO buffer full or request queue

At least one isochronous OUT endpoint is pending at the end of the

At least one isochronous IN endpoint is pending at the end of the

At least one IN or OUT endpoint interrupt is pending at the end of the

The end of the periodic frame is reached.

Failure to write an isochronous OUT packet to the RX FIFO buffer. The

RX FIFO buffer does not have enough space to accommodate the

maximum packet size for the isochronous OUT endpoint.

Enumeration has completed.

Connector ID change.

Mode mismatch. Software accesses registers belonging to an incorrect

Nonperiodic TX FIFO buffer is empty.

RX FIFO buffer is not empty.

Start of microframe.

Device connection debounce is complete in host mode.

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Common modes

OTG interrupts

USB 2.0 OTG Controller

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