Altera cyclone V Technical Reference page 2104

18-14
Host Transaction
The controller waits for a connection to be detected on the USB link.
2. When a USB device connects, an interrupt is generated. The Port Connect Detected (
in
hprt
3. Upon detecting a port connection, the software driver initiates a port reset by setting the Port Reset
(
prtrst
4. The software driver must wait a minimum of 10 ms so that speed enumeration can complete on the
USB link.
5. After the 10 ms, the software driver sets
6. The USB OTG controller generates an interrupt. The Port Enable Disable Change (
Port Speed (
At this point the port is enabled for communication. Keep alive or SOF packets are sent on the port. If a
USB 2.0-capable device fails to initialize correctly, it is reported as a USB 1.1 device.
The Host Frame Interval Register (
, used for sending SOF packets, is in the Host Mode Registers (
hfir
7. The software driver must program the following registers in the Global Registers (
the order listed:
a. Receive FIFO Size Register (
b. Non-periodic Transmit FIFO Size Register (
the non-periodic transmit FIFO buffer for nonperiodic transactions
c. Host Periodic Transmit FIFO Size Register (
periodic transmit FIFO buffer for periodic transactions
8. System software initializes and enables at least one channel to communicate with the USB device.
Host Transaction
When configured as a host, the USB OTG controller pipes the USB transactions through one of two
request queues (one for periodic transactions and one for nonperiodic transactions). Each entry in the
request queue holds the SETUP, IN, or OUT channel number along with other information required to
perform a transaction on the USB link. The sequence in which the requests are written to the queue
determines the sequence of transactions on the USB link.
The host processes the requests in the following order at the beginning of each frame or microframe:
1. Periodic request queue, including isochronous and interrupt transactions
2. Nonperiodic request queue (bulk or control transfers)
The host schedules transactions for each enabled channel in round-robin fashion. When the host
controller completes the transfer for a channel, the controller updates the DMA descriptor status in the
system memory.
For OUT transactions, the host controller uses two transmit FIFO buffers to hold the packet payload to be
transmitted. One transmit FIFO buffer is used for all nonperiodic OUT transactions and the other is used
for all periodic OUT transactions.
For IN transactions, the USB host controller uses one receive FIFO buffer for all periodic and nonperiodic
transactions. The controller holds the packet payload from the USB device in the receive FIFO buffer until
the packet is transferred to the system memory. The receive FIFO buffer also holds the status of each
packet received. The status entry holds the IN channel number along with other information, including
received byte count and validity status.
Altera Corporation
is set to 1.
) bit to 1 in .
hprt
) bits, in
prtspd hprt
grxfsiz
back to 0 to release the port reset.
prtrst
, are set to reflect the enumerated speed of the device that attached.
) is updated with the corresponding PHY clock settings. The
hfir
)—selects the size of the receive FIFO buffer
gnptxfsiz
)—selects the size and start address of the
hptxfsiz
prtenchng
) group.
host grp
globgrp
)—selects the size and the start address of
cv_5v4
2016.10.28
) bit
PrtConnDet
) and
) group, in
USB 2.0 OTG Controller
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