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Renesas H8/3039 Series Hardware Manual

16-bit single-chip microcomputer

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H8/3039

16

Rev.3.00

Revision date: Mar. 26, 2007

,

H8/3039F-ZTAT™

Group

Renesas 16-Bit Single-Chip Microcomputer

H8/3039 HD64F3039F

HD64F3039TE

HD64F3039VF

HD64F3039VTE

HD6433039F

HD6433039TE

HD6433039VF

HD6433039VTE

H8/3038 HD6433038F

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HD6433038VF

HD6433038VTE

Hardware Manual

H8 Family / H8/300H Series

H8/3037 HD6433037F

HD6433037TE

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HD6433037VTE

H8/3036 HD6433036F

HD6433036TE

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Summary of Contents for Renesas H8/3039 Series

Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3039 H8/3039F-ZTAT™ Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series H8/3037 HD6433037F H8/3039 HD64F3039F HD6433037TE HD64F3039TE HD6433037VF...
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3: General Precautions In The Handling Of Mpu/Mcu Products
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Rev.3.00 Mar. 26, 2007 Page iv of xxii REJ09B0353-0300...
Page 5 This manual describes the H8/3039 Group hardware. For details of the instruction set, refer to the H8/300H Series Software Manual. Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page v of xxii REJ09B0353-0300...
Page 6 Rev.3.00 Mar. 26, 2007 Page vi of xxii REJ09B0353-0300...
Page 7 Page Revision (See Manual for Details) • — Notification of change in company name amended (Before) Hitachi, Ltd. → (After) Renesas Technology Corp. • Product naming convention amended (Before) H8/3039 Series → (After) H8/3039 Group 2.3 Address Space Figure amended Figure 2.2 Memory...
Page 8 Item Page Revision (See Manual for Details) 5.3.3 Interrupt Vector Table amended Table WOVI (interval timer) Table 5.3 Interrupt Sources, Vector Addresses, and Priority 5.5.4 Usage Notes Figure amended Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed 1 read 0 written 1 read written...
Page 9 Item Page Revision (See Manual for Details) 16.2.1 Connecting a Preliminary deleted Crystal Resonator Table 16.2 Crystal Resonator Parameters 18.1.3 AC Table amended Characteristics Condition A Condition B Condition C 8 MHz 10 MHz 18 MHz Table 18.5 Control Item Symbol Unit Test Conditions...
Page 10 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Mar. 26, 2007 Page x of xxii REJ09B0353-0300...
Page 11: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... Pin Functions ........................12 Section 2 CPU ........................17 Overview........................... 17 2.1.1 Features........................ 17 2.1.2 Differences from H8/300 CPU................18 CPU Operating Modes ...................... 19 Address Space ........................
Page 12 2.8.6 Power-Down State ....................53 Basic Operational Timing ....................54 2.9.1 Overview......................54 2.9.2 On-Chip Memory Access Timing................ 54 2.9.3 On-Chip Supporting Module Access Timing ............55 2.9.4 Access to External Address Space ............... 56 Section 3 MCU Operating Modes ..................
Page 13 5.1.3 Pin Configuration....................85 5.1.4 Register Configuration..................85 Register Descriptions ......................86 5.2.1 System Control Register (SYSCR) ..............86 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ..........88 5.2.3 IRQ Status Register (ISR)..................93 5.2.4 IRQ Enable Register (IER) .................. 94 5.2.5 IRQ Sense Control Register (ISCR) ..............
Page 14 Section 7 I/O Ports ......................133 Overview........................... 133 Port 1..........................137 7.2.1 Overview......................137 7.2.2 Register Descriptions ................... 138 7.2.3 Pin Functions in Each Mode ................140 Port 2..........................142 7.3.1 Overview......................142 7.3.2 Register Descriptions ................... 143 7.3.3 Pin Functions in Each Mode ................145 7.3.4 Input Pull-Up Transistors..................
Page 15 7.11.2 Register Descriptions ................... 182 7.11.3 Pin Functions ....................... 184 Section 8 16-Bit Integrated Timer Unit (ITU) ............191 Overview........................... 191 8.1.1 Features........................ 191 8.1.2 Block Diagrams ....................194 8.1.3 Input/Output Pins ....................199 8.1.4 Register Configuration..................201 Register Descriptions ......................204 8.2.1 Timer Start Register (TSTR)................
Page 16 Section 9 Programmable Timing Pattern Controller ..........291 Overview........................... 291 9.1.1 Features........................ 291 9.1.2 Block Diagram..................... 292 9.1.3 TPC Pins ......................293 9.1.4 Registers....................... 294 Register Descriptions ......................295 9.2.1 Port A Data Direction Register (PADDR) ............295 9.2.2 Port A Data Register (PADR)................295 9.2.3 Port B Data Direction Register (PBDDR) ............
Page 17 10.3.3 Timing of Setting of Overflow Flag (OVF) ............328 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)........329 10.4 Interrupts ........................... 329 10.5 Usage Notes ........................330 Section 11 Serial Communication Interface ..............331 11.1 Overview........................... 331 11.1.1 Features........................
Page 18 12.3.4 Register Settings ....................401 12.3.5 Clock........................403 12.3.6 Data Transfer Operations..................405 12.4 Usage Note........................411 Section 13 A/D Converter ....................415 13.1 Overview........................... 415 13.1.1 Features........................ 415 13.1.2 Block Diagram..................... 416 13.1.3 Input Pins ......................417 13.1.4 Register Configuration..................418 13.2 Register Descriptions ......................
Page 19 15.3.3 RAM Control Register (RAMCR) ............... 449 15.3.4 Flash Memory Status Register (FLMSR)............. 451 15.4 On-Board Programming Modes..................452 15.4.1 Boot Mode ......................455 15.4.2 User Program Mode..................... 460 15.5 Programming/Erasing Flash Memory ................462 15.5.1 Program Mode ..................... 463 15.5.2 Program-Verify Mode..................
Page 20 16.5.2 Division Control Register (DIVCR) ..............505 16.5.3 Usage Notes ......................506 Section 17 Power-Down State ..................507 17.1 Overview........................... 507 17.2 Register Configuration...................... 509 17.2.1 System Control Register (SYSCR) ..............509 17.2.2 Module Standby Control Register (MSTCR) ............511 17.3 Sleep Mode ........................
Page 21 18.3.2 Control Signal Timing ..................556 18.3.3 Clock Timing ....................... 558 18.3.4 TPC and I/O Port Timing..................558 18.3.5 ITU Timing ......................559 18.3.6 SCI Input/Output Timing ..................560 Appendix A Instruction Set ....................561 Instruction List ........................561 Operation Code Maps ....................... 577 Number of States Required for Execution ................
Page 22 Rev.3.00 Mar. 26, 2007 Page xxii of xxii REJ09B0353-0300...
Page 23: Section 1 Overview
Section 1 Overview Overview The H8/3039 Group comprises microcomputers (MCUs) that integrate system supporting functions together with an H8/300H CPU core featuring an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed.
Page 24 Section 1 Overview Table 1.1 Features Feature Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine • Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation • Maximum clock rate: 18 MHz •...
Page 25 Section 1 Overview Feature Description Memory H8/3039 • ROM: 128 kbytes • RAM: 4 kbytes H8/3038 • ROM: 64 kbytes • RAM: 2 kbytes H8/3037 • ROM: 32 kbytes • RAM: 1 kbyte H8/3036 • ROM: 16 kbytes • RAM: 512 bytes Five external interrupt pins: NMI, IRQ , IRQ , IRQ...
Page 26 Section 1 Overview Feature Description • Programmable Maximum 15-bit pulse output, using ITU as time base timing pattern • Up to three 4-bit pulse output groups and one 3-bit pulse output group (or controller (TPC) one 15-bit group, one 8-bit group, or one 7-bit group) •...
Page 27 Section 1 Overview Feature Description • Other features On-chip clock oscillator Product lineup Model (5 V) Model (3 V)* Package HD64F3039F HD64F3039VF 80-pin QFP (FP-80A) Flash memory HD64F3039TE HD64F3039VTE 80-pin TQFP (TFP-80C) HD6433039F HD6433039VF 80-pin QFP (FP-80A) Mask ROM HD6433039TE HD6433039VTE 80-pin TQFP (TFP-80C) HD6433038F...
Page 28: Block Diagram
Section 1 Overview Block Diagram Figure 1.1 shows an internal block diagram of the H8/3039 Group. Port 3 Address bus Data bus (upper) Data bus (lower) EXTAL XTAL φ H8/300H CPU STBY RESO/FWE * Interrupt controller (Flash memory, mask ROM) /WAIT Watchdog timer...
Page 29: Pin Description
Section 1 Overview Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8/3039 Group. TIOCA TIOCB TIOCA RESO/FWE * TIOCB TOCXA TOCXB ADTRG/TP XTAL Top view EXTAL (FP-80A, TFP-80C) /SCK STBY φ /WAIT Note: * Mask ROM: RESO Flash memory: FWE Figure 1.2 Pin Arrangement (FP-80A, TFP-80C Top View) Rev.3.00 Mar.
Page 30: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Pin Assignments in Each Mode Table 1.2 lists the FP-80A and TFP-80C pin assignments in each mode. Table 1.2 FP-80A and TFP-80C Pin Assignments in Each Mode Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7...
Page 31 Section 1 Overview Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Flash memory /WAIT /WAIT /WAIT φ φ φ φ φ Rev.3.00 Mar. 26, 2007 Page 9 of 682 REJ09B0353-0300...
Page 32 Section 1 Overview Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Flash memory STBY STBY STBY STBY STBY EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL XTAL XTAL XTAL XTAL XTAL XTAL RESO/ RESO/ RESO/ RESO/ RESO/ FWE* FWE*...
Page 33 Section 1 Overview Pin Name PROM Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Flash memory TCLKB TCLKB TCLKB TCLKB TCLKB TIOCA TIOCA TIOCA TIOCA TIOCA TCLKC TCLKC TCLKC TCLKC TCLKC TIOCB TIOCB TIOCB TIOCB TIOCB TCLKD TCLKD TCLKD TCLKD...
Page 34: Pin Functions
Section 1 Overview Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Pin Functions Type Symbol Pin No. Name and Function Power Input Power: For connection to the power supply. Connect all V pins to the system power supply. Input Ground: For connection to ground (0 V).
Page 35 Section 1 Overview Type Symbol Pin No. Name and Function System Input Reset input: When driven low, this pin resets control the chip RESO/ Output/ Reset output (Mask ROM version): Outputs Input WDT-generated reset signal to an external device. Write enable signal (F-ZTAT version): Flash memory write control signal.
Page 36 Section 1 Overview Type Symbol Pin No. Name and Function Programmable 8, 6 to 1 Output TPC output 15, 13 to 0 : Pulse output timing pattern to TP 80 to 73 controller (TPC) Serial com- 70, 9 Output Transmit data:(channels 0 and 1): SCI data munication output interface...
Page 37 Section 1 Overview Type Symbol Pin No. Name and Function I/O ports 72, 11 Input/ Port 9: Six input/output pins. The direction of 71, 10 output each pin can be selected in the port 9 data 70, 9 direction register (P9DDR). 80 to 73 Input/ Port A: Eight input/output pins.
Page 38 Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 16 of 682 REJ09B0353-0300...
Page 39: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features.
Page 40: Differences From H8/300 Cpu
Section 2 CPU  16 × 16-bit register-register multiply: 1222 ns  32 ÷ 16-bit register-register divide: 1222 ns • Two CPU operating modes  Normal mode  Advanced mode • Low-power mode Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
Page 41: Cpu Operating Modes
Section 2 CPU CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1. Unless specified otherwise, all descriptions in this manual refer to advanced mode. Maximum 64 kbytes, program Normal mode and data areas combined...
Page 42: Address Space
Section 2 CPU Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of a normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address space depending on the MCU operation mode. Figure 2.2 shows the address ranges of the H8/3039 Group.
Page 43: Register Configuration
Section 2 CPU Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) (SP) Control Registers (CR) 6 5 4 3 2 1 0 I UI H U N Z V C Legend: Stack pointer...
Page 44: General Registers
Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).
Page 45: Control Registers
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers...
Page 46: Initial Cpu Register Values
Section 2 CPU Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
Page 47: Data Formats
Section 2 CPU Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 48 Section 2 CPU General Data Type Register Data Format Word data Word data Longword data Legend: ERn: General register General register E General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats Rev.3.00 Mar. 26, 2007 Page 26 of 682 REJ09B0353-0300...
Page 49: Memory Data Formats
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 50: Instruction Set
Section 2 CPU Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified as shown in table 2.1. Table 2.1 Instruction Classification Function Instruction Types Data transfer MOV, PUSH* , POP* , MOVTPE* , MOVFPE* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,...
Page 51: Instructions And Addressing Modes
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes Function Instruction Data BWL BWL BWL BWL BWL BWL BWL BWL — — — —...
Page 52 Section 2 CPU Addressing Modes Function Instruction System TRAPA — — — — — — — — — — — — control — — — — — — — — — — — — SLEEP — — — — — —...
Page 53: Tables Of Instructions Classified By Function
Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined as follows. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register or address register) (EAd)
Page 54 Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. (EAs) → Rd MOVFPE Cannot be used in the H8/3039 Group.
Page 55 Section 2 CPU Table 2.4 Arithmetic Operation Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD, B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register.
Page 56 Section 2 CPU Instruction Size* Function Rd ÷ Rs → Rd DIVXU Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Page 57 Section 2 CPU Table 2.5 Logic Operation Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 58 Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.
Page 59 Section 2 CPU Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>)] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry...
Page 60 Section 2 CPU Table 2.8 Branching Instructions Instruction Size Function — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨...
Page 61 Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state (EAs) → CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access.
Page 62: Basic Instruction Formats
Section 2 CPU Table 2.10 Block Transfer Instruction Instruction Size Function if R4L ≠ 0 then EEPMOV.B — @ER5+ → @ER6+, R4L – 1 → R4L repeat until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W @ER5+ → @ER6+, R4 – 1 → R4 repeat until R4 = 0...
Page 63: Notes On Use Of Bit Manipulation Instructions
Section 2 CPU Figure 2.9 shows examples of instruction formats. Operation field only NOP, RTS, etc. Operation field and register fields ADD.B Rn, Rm, etc. Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm EA (disp) Operation field, effective address extension, and condition field EA (disp) BRA d:8 Figure 2.9 Instruction Formats...
Page 64 Section 2 CPU BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16, ERn)/@d:24, ERn) Register indirect with post-increment @Ern+ Register indirect with pre-decrement...
Page 65 Section 2 CPU 4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register.
Page 66 Section 2 CPU 6. Immediate—#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number.
Page 67: Effective Address Calculation
Section 2 CPU When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats.
Page 68 Section 2 CPU Table 2.13 Effective Address Calculation Rev.3.00 Mar. 26, 2007 Page 46 of 682 REJ09B0353-0300...
Page 69 Section 2 CPU Rev.3.00 Mar. 26, 2007 Page 47 of 682 REJ09B0353-0300...
Page 70 Section 2 CPU Rev.3.00 Mar. 26, 2007 Page 48 of 682 REJ09B0353-0300...
Page 71: Processing States
Section 2 CPU Processing States 2.8.1 Overview The H8/300H CPU has four processing states: the program execution state, exception-handling state, power-down state, and reset state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions.
Page 72: Exception-Handling State
Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register.
Page 73: Exception-Handling Sequences
Section 2 CPU Reset External interrupts Exception Interrupt sources Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.12 Classification of Exception Sources Program execution state SLEEP instruction with SSBY = 0 Exception End of exception Sleep mode handling SLEEP instruction Interrupt with SSBY = 1 NMI, IRQ , IRQ ,...
Page 74 Section 2 CPU including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack.
Page 75: Reset State
Section 2 CPU 2.8.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high.
Page 76: Basic Operational Timing
Section 2 CPU Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of two or three states.
Page 77: On-Chip Supporting Module Access Timing
Section 2 CPU φ Address bus Address , RD, WR High High impedance to D Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed.
Page 78: Access To External Address Space
Section 2 CPU φ Address bus Address , RD, WR High High impedance to D Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area accessed in two or three states.
Page 79: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection The H8/3039 Group has five operating modes (modes 1, 3, 5 to7) that are selected by the mode pins (MD to MD ) as indicated in table 3.1. The input at these pins determines expanded mode or single-chip mode.
Page 80: Register Configuration
Section 3 MCU Operating Modes Mode 5 is externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers. All I/O ports are available.
Page 81: Mode Control Register (Mdcr)
Section 3 MCU Operating Modes Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3039 Group. — — — — — MDS2 MDS1 MDS0 Initial value — — — Read/Write — —...
Page 82: System Control Register (Syscr)
Section 3 MCU Operating Modes System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3039 Group. SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select Selects the valid edge...
Page 83 Section 3 MCU Operating Modes least 7 ms at the system clock rate. For further information about waiting time selection, see section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode. Bit 6 Bit 5 Bit 4 STS2 STS1 STS0...
Page 84: Operating Mode Descriptions
Section 3 MCU Operating Modes Operating Mode Descriptions 3.4.1 Mode 1 Ports 1, 2, and 5 function as address pins A to A , permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. 3.4.2 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A...
Page 85: Pin Functions In Each Operating Mode
Section 3 MCU Operating Modes Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, port 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1...
Page 86 Section 3 MCU Operating Modes Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'200000 H'3FFFF...
Page 87 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'07FFF...
Page 88 Section 3 MCU Operating Modes Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000...
Page 89 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'F70F...
Page 90 Section 3 MCU Operating Modes Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000...
Page 91 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'07FFF H'7FFF...
Page 92 Section 3 MCU Operating Modes Mode 1 Mode 3 (1-Mbyte expanded modes with (16-Mbyte expanded modes with on-chip ROM disabled) on-chip ROM disabled) H'00000 H'000000 Vector area Vector area H'000FF H'0000FF H'07FFF H'007FFF Area 0 Area 0 H'1FFFF H'20000 H'1FFFFF Area 1 H'3FFFF H'200000...
Page 93 Section 3 MCU Operating Modes Mode 5 Mode 6 Mode 7 (1-Mbyte expanded mode with (single-chip normal mode) (single-chip advanced mode) on-chip ROM enabled) H'00000 H'0000 H'00000 Vector area Vector area Vector area H'000FF H'00FF H'000FF On-chip ROM On-chip ROM On-chip ROM H'03FFF H'03FFF...
Page 94: Restrictions On Use Of Mode 6
Section 3 MCU Operating Modes Restrictions on Use of Mode 6 In mode 6 (single-chip normal mode), on-chip ROM area data is undefined if address H'10000 or above (64 kbytes or above) is accessed, and therefore instruction code fetch and data read operations may not always be performed normally.
Page 95 Section 3 MCU Operating Modes Conditions Addressing Mode Restricted Item Address Range Operation Restriction Absolute address Value of @aa H'010000 or Read data is Do not access (@aa:24) above, with lower undefined. addresses in range 16 bits in range Writes are shown under conditions;...
Page 96 Section 3 MCU Operating Modes Rev.3.00 Mar. 26, 2007 Page 74 of 682 REJ09B0353-0300...
Page 97: Section 4 Exception Handling
Section 4 Exception Handling Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order.
Page 98: Exception Vector Table
Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. • Reset External interrupts: NMI, IRQ , IRQ , IRQ...
Page 99 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* Exception Source Vector Number Normal Mode Advanced Mode Reset H'0000 to H'0001 H'0000 to H'0003 Reserved for system use H'0002 to H'0003 H'0004 to H'0007 H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F H'0008 to H'0009...
Page 100: Reset
Section 4 Exception Handling Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the H8/3039 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules.
Page 101 Section 4 Exception Handling Figure 4.2 Reset Sequence (Modes 5 and 7) Rev.3.00 Mar. 26, 2007 Page 79 of 682 REJ09B0353-0300...
Page 102: Interrupts After Reset
Section 4 Exception Handling 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 103: Trap Instruction
Section 4 Exception Handling Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR.
Page 104: Notes On Stack Usage
Section 4 Exception Handling Notes on Stack Usage When accessing word data or longword data, the H8/3039 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 105: Section 5 Interrupt Controller
Section 5 Interrupt Controller Section 5 Interrupt Controller Overview 5.1.1 Features The interrupt controller has the following features: • Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB).
Page 106: Block Diagram
Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR IPRA, IPRB input IRQ input IRQ input section ISR Interrupt request Priority decision logic Vector number ADIE Interrupt controller SYSCR Legend: Interrupt mask bit IER: IRQ enable register IPRA:...
Page 107: Pin Configuration
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable interrupt, rising edge or falling edge selectable , IRQ External interrupt , and Input Maskable interrupts, falling edge or level , IRQ request 5, 4, 1, and 0 sensing selectable...
Page 108: Register Descriptions
Section 5 Interrupt Controller Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here.
Page 109 Section 5 Interrupt Controller Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2—NMI Edge Select (NMIEG): Selects the NMI input edge.
Page 110: Interrupt Priority Registers A And B (Ipra, Iprb)
Section 5 Interrupt Controller 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Interrupt Priority Register A (IPRA) IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRA7 IPRA6 —...
Page 111 Section 5 Interrupt Controller IPRA is initialized to H'00 by a reset and in hardware standby mode. Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit7 IPRA7 Description IRQ0 interrupt requests have priority level 0 (low priority) (Initial value) IRQ0 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests.
Page 112 Section 5 Interrupt Controller Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit2 IPRA2 Description ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 0 interrupt requests have priority level 1 (high priority) Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Page 113 Section 5 Interrupt Controller Interrupt Priority Register B (IPRB) IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. IPRB7 IPRB6 — — IPRB3 IPRB2 IPRB1 — Initial value Read/Write Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2...
Page 114 Section 5 Interrupt Controller Bit 7—Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit7 IPRB7 Description ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value) ITU channel 3 interrupt requests have priority level 1 (high priority) Bit 6—Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests.
Page 115: Irq Status Register (Isr)
Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ , IRQ , IRQ , and IRQ interrupt requests. — — IRQ5F IRQ4F — — IRQ1F IRQ0F Initial value R/(W) * R/(W) * R/(W) *...
Page 116: Irq Enable Register (Ier)
Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ , IRQ , IRQ , and IRQ interrupt requests. — — IRQ5E IRQ4E — — IRQ1E IRQ0E Initial value Read/Write Reserved bits Reserved bits to IRQ...
Page 117: Irq Sense Control Register (Iscr)
Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ , IRQ , IRQ , and IRQ — — IRQ5SC IRQ4SC —...
Page 118: Interrupt Sources
Section 5 Interrupt Controller Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ , IRQ , IRQ and IRQ ) and 25 internal interrupts. 5.3.1 External Interrupts There are five external interrupts: NMI, and IRQ , IRQ , IRQ , and IRQ .
Page 119: Internal Interrupts
Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). φ IRQn input pin IRQnF Note: n = 5, 4, 1 and 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ , IRQ , IRQ , IRQ have vector numbers 17, 16, 13, 12.
Page 120 Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Address* Vector Interrupt Source Origin Number Normal Mode Advanced Mode Priority External pins H'000E to H'000F H'001C to H'001F — High H'0018 to H'0019 H'0030 to H'0033 IPRA7 H'001A to H'001B H'0034 to H0037 IPRA6...
Page 121 Section 5 Interrupt Controller Vector Address* Vector Interrupt Source Origin Number Normal Mode Advanced Mode Priority IMIA3 (compare match/ ITU channel 3 H'0048 to H'0049 H'0090 to H'0093 IPRB7 input capture A3) IMIB3 (compare match/ H'004A to H'004B H'0094 to H'0097 input capture B3) OVI3 (overflow 3) H'004C to H'004D...
Page 122: Interrupt Operation
Section 5 Interrupt Controller Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3039 Group handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Page 123 Section 5 Interrupt Controller Program execution state Interrupt requested? NMI? Pending Priority level 1? ADI? ADI? I = 0? Save PC and CCR ← Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev.3.00 Mar.
Page 124 Section 5 Interrupt Controller • If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. • When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, following the IPR interrupt priority settings, and holds other requests pending.
Page 125 Section 5 Interrupt Controller ← All interrupts are Only NMI, IRQ , and ← ← 1, UI unmasked IRQ are unmasked Exception handling, ← ← or I 1, UI ← ← Exception handling, ← or UI All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
Page 126 Section 5 Interrupt Controller Program execution state Interrupt requested? NMI? Pending Priority level 1? ADI? ADI? I = 0? I = 0? UI = 0? Save PC and CCR ← ← 1, UI Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev.3.00 Mar.
Page 127: Interrupt Sequence
Section 5 Interrupt Controller 5.4.2 Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 5 when the program code and stack are in an on- chip memory area. Figure 5.7 Interrupt Sequence (Mode 5, Stack in On-Chip Memory) Rev.3.00 Mar. 26, 2007 Page 105 of 682 REJ09B0353-0300...
Page 128: Interrupt Response Time
Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory 8-Bit Bus On-Chip Item...
Page 129: Usage Notes
Section 5 Interrupt Controller Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out.
Page 130: Instructions That Inhibit Interrupts
Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction.
Page 131 Section 5 Interrupt Controller 2. Generation Conditions (1) A read of the ISR register is executed to clear the IRQaF flag while it is set to 1, then the IRQbF flag is cleared by the execution of interrupt exception handling. (2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag setting).
Page 132 Section 5 Interrupt Controller Either of the methods shown below should be used to prevent this problem. Method 1: When clearing the IRQaF flag, read ISR as a byte unit instead of using a bit- manipulation instruction, and write a byte value that clears the IRQaF flag to 0 and sets the other bits to 1.
Page 133: Section 6 Bus Controller
Section 6 Bus Controller Section 6 Bus Controller Overview The H8/3039 Group has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily.
Page 134: Block Diagram
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. ASTCR Internal WCER address bus Area Internal signals decoder Access state control signal Bus control circuit Wait request signal Wait-state WAIT controller Legend: ASTCR: Access state control register WCER:...
Page 135: Input/Output Pins
Section 6 Bus Controller 6.1.3 Input/Output Pins Table 6.1 summarizes the bus controller's input/output pins. Table 6.1 Bus Controller Pins Name Abbreviation Function Address strobe Output Strobe signal indicating valid address output on the address bus Read Output Strobe signal indicating reading from the external address space Write Output...
Page 136: Register Descriptions
Section 6 Bus Controller Register Descriptions 6.2.1 Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode.
Page 137: Wait Control Register (Wcr)
Section 6 Bus Controller 6.2.2 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. — — — — WMS1 WMS0 Initial value Read/Write —...
Page 138: Wait State Controller Enable Register (Wcer)
Section 6 Bus Controller Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit1 Bit0 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value)
Page 139: Address Control Register (Adrcr)
Section 6 Bus Controller 6.2.4 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21. — — — — — Initial value Modes 1 and 5 to 7 Read/Write — —...
Page 140 Section 6 Bus Controller Bit 5—Address 21 Enable (A E): Enables PA to be used as the A address output pin. Writing 0 in this bit enables A address output from PA . In modes other than 3 this bit cannot be modified and PA has its ordinary input/output functions.
Page 141: Operation
Section 6 Bus Controller Operation 6.3.1 Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6.2 shows a general view of the memory map.
Page 142 Section 6 Bus Controller The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 Bus Specifications ASTCR WCER Bus Specifications Access ASTn WCEn WMS1 WMS0 Width States Wait Mode —...
Page 143: Bus Control Signal Timing
Section 6 Bus Controller 6.3.2 Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.3 shows the timing of bus control signals for an 8-bit, three-state-access area. Wait states can be inserted. Bus cycle φ Address bus External address Read access Valid to D Write...
Page 144 Section 6 Bus Controller 8-Bit, Two-State-Access Areas Figure 6.4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait states cannot be inserted. Bus cycle φ Address bus External address Read access to D Valid Write access to D Valid Figure 6.4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area...
Page 145: Wait Modes
Section 6 Bus Controller 6.3.3 Wait Modes Four wait modes can be selected for each area as shown in table 6.4. Table 6.4 Wait Mode Selection ASTCR WCER ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode —...
Page 146 Section 6 Bus Controller Pin Wait Mode 0 The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall of the system clock ) is inserted.
Page 147 Section 6 Bus Controller Pin Wait Mode 1 In all accesses to external three-state-access areas, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (φ) in the last of these wait states, an additional wait state is inserted.
Page 148 Section 6 Bus Controller Pin Auto-Wait Mode If the WAIT pin is low, the number of wait states (T ) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (φ) in the T state, the number of wait states (T ) selected by bits WC1 and WC0 are inserted.
Page 149 Section 6 Bus Controller Programmable Wait Mode The number of wait states (T ) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6.8 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1).
Page 150 Section 6 Bus Controller Example of Wait State Control Settings A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings.
Page 151: Interconnections With Memory (Example)
Section 6 Bus Controller 6.3.4 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices.
Page 152 Section 6 Bus Controller H'00000 On-chip ROM Area 0 H'1FFFF H'20000 Area 1 H'3FFFF H'40000 EPROM H'47FFF Area 2 H'48000 8-bit, three-state-access area Not used H'5FFFF H'60000 SRAM1, 2 Area 3 H'6FFFF 8-bit, two-state-access area H'70000 Not used H'7FFFF Areas 4, 5, 6 H'E0000 SRAM3 H'E7FFF...
Page 153: Usage Notes
Section 6 Bus Controller Usage Notes 6.4.1 Register Write Timing ASTCR and WCER Write Timing Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6.11 shows the timing when an instruction fetched from area 2 changes area 2 from three-state access to two- state access.
Page 154 Section 6 Bus Controller Rev.3.00 Mar. 26, 2007 Page 132 of 682 REJ09B0353-0300...
Page 155: Section 7 I/O Ports
Section 7 I/O Ports Section 7 I/O Ports Overview The H8/3039 Group has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1.
Page 156 Section 7 I/O Ports Table 7.1 Port Functions Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O port to P1 Address output Address output Generic input/ output to A pins (A to A to A ) and...
Page 157 Section 7 I/O Ports Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port 9 • 6-bit I/O Input and output (SCK , SCK , RxD , RxD , TxD , TxD ) for serial /SCK /IRQ communication interfaces 1 and 0 (SCI0, 1), IRQ and IRQ...
Page 158 Section 7 I/O Ports Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port B • 7-bit I/Oport TPC output (TP ), trigger input (ADTRG) to A/D converter, and generic ADTRG input/output. • Can drive LEDs TPC output (TP to TP ), ITU input and output (TOCXB...
Page 159: Port 1
Section 7 I/O Ports Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), they are address bus output pins (A to A In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction...
Page 160: Register Descriptions
Section 7 I/O Ports 7.2.2 Register Descriptions Table 7.2 summarizes the registers of port 1. Table 7.2 Port 1 Registers Initial Value Address* Name Abbreviation Modes 1, 3 Modes 5 to 7 H'FFC0 Port 1 data direction P1DDR H'FF H'00 register H'FFC2 Port 1 data register...
Page 161 Section 7 I/O Ports Port 1 Data Register (P1DR) P1DR is an 8-bit readable/writable register that stores data for pins P1 to P1 Initial value Read/Write Port 1 data 7 to 0 These bits store data for port 1 pins When a bit in P1DDR is set to 1, if port 1 is read the value of the corresponding P1DR bit is returned directly, regardless of the actual state of the pin.
Page 162: Pin Functions In Each Mode
Section 7 I/O Ports 7.2.3 Pin Functions in Each Mode The pin functions of port 1 differ between mode 1, 3 (expanded mode with on-chip ROM disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip mode).
Page 163 Section 7 I/O Ports When P1DDR = 1 When P1DDR = 0 A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) Port 1 A (output) P1 (input) A (output) P1 (input) A (output) P1 (input) A (output) P1 (input)
Page 164: Port 2
Section 7 I/O Ports Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. Pin functions differ according to operation mode. In modes 1 and 3 (expanded mode with on-chip ROM disabled), port 2 consists of address bus output pins (A to A ).
Page 165: Register Descriptions
Section 7 I/O Ports 7.3.2 Register Descriptions Table 7.3 summarizes the registers of port 2. Table 7.3 Port 2 Registers Initial Value Address* Name Abbreviation Modes 1 and 3 Modes 5 to 7 H'FFC1 Port 2 data direction P2DDR H'FF H'00 register H'FFC3...
Page 166 Section 7 I/O Ports Port 2 Data Register (P2DR) P2DR is an 8-bit readable/writable register that stores data for pins P2 to P2 Initial value Read/Write Port 2 data 7 to 0 These bits store data for port 2 pins When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned directly, regardless of the actual state of the pin.
Page 167: Pin Functions In Each Mode
Section 7 I/O Ports 7.3.3 Pin Functions in Each Mode The pin functions of port 2 differ between mode 1, 3 (expanded mode with on-chip ROM disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip mode).
Page 168 Section 7 I/O Ports When P2DDR = 1 When P2DDR = 0 (output) P2 (input) (output) P2 (input) (output) P2 (input) (output) P2 (input) Port 2 (output) P2 (input) (output) P2 (input) A (output) P2 (input) A (output) P2 (input) Figure 7.7 Pin Functions in Modes 1 and 3 (Port 2) Modes 6 and 7 Input or output can be selected separately for each pin in port 2.
Page 169: Input Pull-Up Transistors
Section 7 I/O Ports 7.3.4 Input Pull-Up Transistors Port 2 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up transistor is turned on.
Page 170: Port 3
Section 7 I/O Ports Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7.9. Port 3 is a data bus in modes 1, 3 and 5 (expanded modes) and a generic input/output port in mode 6 and 7 (single-chip mode).
Page 171 Section 7 I/O Ports Port 3 Data Direction Register (P3DDR) P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value...
Page 172: Pin Functions In Each Mode
Section 7 I/O Ports 7.4.3 Pin Functions in Each Mode The pin functions of port 3 differ between modes 1, 3 and 5 and modes 6 and 7. The pin functions in each mode are described below. Modes 1, 3 and 5 All pins of port 3 automatically become data input/output pins.
Page 173 Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 3. A pin becomes an output pin if the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.11 shows the pin functions in modes 6 and 7.
Page 174: Port 5
Section 7 I/O Ports Port 5 7.5.1 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7.12. The pin functions differ depending on the operating mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A19 to A16).
Page 175: Register Descriptions
Section 7 I/O Ports 7.5.2 Register Descriptions Table 7.6 summarizes the registers of port 5. Table 7.6 Port 5 Registers Initial Value Address* Name Abbreviation Modes 1 and 3 Modes 5 to 7 H'FFC8 Port 5 data direction P5DDR H'FF H'F0 register H'FFCA...
Page 176 Section 7 I/O Ports Port 5 Data Register (P5DR) P5DR is an 8-bit readable/writable register that stores data for pins P5 to P5 — — — — Initial value Read/Write — — — — Reserved bits Port 5 data 3 to 0 These bits store data for port 5 pins When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is...
Page 177: Pin Functions In Each Mode
Section 7 I/O Ports 7.5.3 Pin Functions in Each Mode The pin functions differ between mode 1, 3 (expanded modes with on-chip ROM disabled), mode 5 (expanded modes with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described below.
Page 178: Input Pull-Up Transistors
Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 5. A pin becomes an output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.15 shows the pin functions in modes 6 and 7.
Page 179: Port 6
Section 7 I/O Ports Port 6 7.6.1 Overview Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR, RD, AS, and WAIT). Figure 7.16 shows the pin configuration of port 6. In modes 1, 3 and 5, the pin functions are WR, RD, AS, and P6 /WAIT.
Page 180: Register Descriptions
Section 7 I/O Ports 7.6.2 Register Descriptions Table 7.8 summarizes the registers of port 6. Table 7.8 Port 6 Registers Initial Value Address* Name Abbreviation Modes 1, 3, and 5 Modes 6 and 7 H'FFC9 Port 6 data direction P6DDR H'F8 H'80 register...
Page 181 Section 7 I/O Ports Port 6 Data Register (P6DR) P6DR is an 8-bit readable/writable register that stores data for pins P6 to P6 and P6 — — — — Initial value Read/Write — Reserved bits Port 6 data 5 to 3, 0 These bits store data for port 6 pins When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly.
Page 182: Pin Functions In Each Mode
Section 7 I/O Ports 7.6.3 Pin Functions in Each Mode Modes 1, 3, and 5 to P6 function as bus control output pins. P6 is either a bus control input pin or generic input/output pin, functioning as an output pin when bit P6 DDR is set to 1 and an input pin when this bit is cleared to 0.
Page 183 Section 7 I/O Ports Table 7.9 Port 6 Pin Functions in Modes 1, 3, and 5 Pin Functions and Selection Method Functions as follows regardless of P6 WR output Pin function Functions as follows regardless of P6 RD output Pin function Functions as follows regardless of P6 AS output Pin function...
Page 184 Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 6. A pin becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.18 shows the pin functions in modes 6 and 7.
Page 185: Port 7
Section 7 I/O Ports Port 7 7.7.1 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin functions are the same in all operating modes. Figure 7.19 shows the pin configuration of port 7. Port 7 pins P7 (input)/AN (input) P7 (input)/AN (input)
Page 186: Port 8
Section 7 I/O Ports Port 7 Data Register (P7DR) Initial value — — — — — — — — Read/Write Note: * Determined by pins P to P When P7DR is read, the pin levels are always read. Port 8 7.8.1 Overview Port 8 is a 2-bit input/output port that is also used for IRQ...
Page 187: Register Descriptions
Section 7 I/O Ports 7.8.2 Register Descriptions Table 7.11 summarizes the registers of port 8. Table 7.11 Port 8 Registers Address* Name Abbreviation Initial Value H'FFCD Port 8 data direction register P8DDR H'E0 H'FFCF Port 8 data register P8DR H'E0 Note: * Lower 16 bits of the address.
Page 188 Section 7 I/O Ports Port 8 Data Register (P8DR) P8DR is an 8-bit readable/writable register that stores data for pins P8 to P8 — — — — — — Initial value Read/Write — — — Reserved bits Port 8 data 1 and 0 These bits store data for port 8 pins When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is...
Page 189: Pin Functions
Section 7 I/O Ports 7.8.3 Pin Functions The port 8 pins are also used for IRQ and IRQ . Table 7.12 describes the selection of pin functions. Table 7.12 Port 8 Pin Functions Pin Functions and Selection Method /IRQ Bit P8 DDR selects the pin function as follows Modes 1, 3, and 5 Modes 6 and 7...
Page 190: Port 9
Section 7 I/O Ports Port 9 7.9.1 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD , TxD , RxD , RxD ) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ , SCK and IRQ input.
Page 191 Section 7 I/O Ports Port 9 Data Direction Register (P9DDR) P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. — — P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR P9 DDR Initial value Read/Write...
Page 192: Pin Functions
Section 7 I/O Ports P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 7.9.3 Pin Functions The port 9 pins are also used for SCI input and output (TxD, RxD, SCK), and for IRQ and IRQ input.
Page 193 Section 7 I/O Ports Pin Functions and Selection Method /RxD Bit RE in SCR of SCI1 and bit P9 DDR select the pin function as follows — Pin function input output input /RxD Bit RE in SCR of SCI , bit SMIF in SCMR, and bit P9 DDR select the pin function as follows SMIF...
Page 194: Port A
Section 7 I/O Ports 7.10 Port A 7.10.1 Overview Port A is an 8-bit input/output port that is also used for output (TP to TP ) from the programmable timing pattern controller (TPC), input and output (TIOCB , TIOCA , TIOCB , TIOCA , TIOCB TIOCA...
Page 195: Register Descriptions
Section 7 I/O Ports 7.10.2 Register Descriptions Table 7.15 summarizes the registers of port A. Table 7.15 Port A Registers Initial Value Address* Name Abbreviation Modes 1, 5, and 7 Mode 3 H'FFD1 Port A data direction PADDR H'00 H'80 register H'FFD3 Port A data register...
Page 196 Section 7 I/O Ports Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores data for pins PA to PA Initial value Read/Write Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly.
Page 197: Pin Functions
Section 7 I/O Ports 7.10.3 Pin Functions The port A pins are also used for TPC output (TP to TP ), ITU input/output (TIOCB to TIOCB TIOCA to TIOCA ) and input (TCLKD, TCLKC, TCLKB, TCLKA), and as address bus pins (A to A ).
Page 198 Section 7 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 2 settings (bit PWM2 in TMDR and TIOCA bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 199 Section 7 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and TIOCB bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 200 Section 7 I/O Ports Pin Functions and Selection Method The mode setting, bit A E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and TIOCB bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA DDR in PADDR select the pin function as follows Mode...
Page 201 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TIOCB TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in TCLKD PADDR select the pin function as follows (1) in table below...
Page 202 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TIOCA TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA DDR in PADDR TCLKC select the pin function as follows...
Page 203 Section 7 I/O Ports Pin Functions and Selection Method Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function as follows TCLKB NDER1 — input output output function TCLKB input* Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0.
Page 204: Port B
Section 7 I/O Ports 7.11 Port B 7.11.1 Overview Port B is a 7-bit input/output port that is also used for TPC output (TP , TP to TP ), ITU input/output (TIOCB , TIOCB , TIOCA , TIOCA ) and ITU output (TOCXB , TOCXA ), and ADTRG input to the A/D converter.
Page 205 Section 7 I/O Ports Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value Read/Write...
Page 206: Pin Functions
Section 7 I/O Ports If bit 6 in PBDDR is read while its value is 1, the value of bit 6 in PBDR will be read directly. If bit 6 in PBDDR is read while its value is 0, it will always be read as 1. PBDR is initialized to H'00 by a reset and in hardware standby mode.
Page 207 Section 7 I/O Ports Table 7.18 Port B Pin Functions Pin Functions and Selection Method Bit TRGE in ADCR, bit NDER15 in NDERB and bit PB7DDR in PBDDR select the pin function as follows ADTRG NDER15 — Pin function input output output ADTRG input*...
Page 208 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB DDR in PBDDR select TIOCB the pin function as follows ITU channel...
Page 209 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB DDR in PBDDR select TIOCA the pin function as follows ITU channel...
Page 210 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and TIOCB bits IOB2 to IOB0 in TIOR3), bit NDER11 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel...
Page 211 Section 7 I/O Ports Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and TIOCA bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB DDR in PBDDR select the pin function as follows ITU channel...
Page 212 Section 7 I/O Ports Rev.3.00 Mar. 26, 2007 Page 190 of 682 REJ09B0353-0300...
Page 213: Section 8 16-Bit Integrated Timer Unit (Itu)
Section 8 16-Bit Integrated Timer Unit (ITU) Section 8 16-Bit Integrated Timer Unit (ITU) Overview The H8/3039 Group has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer channels. 8.1.1 Features ITU features are listed below. • Capability to process up to 12 pulse outputs or 10 pulse inputs •...
Page 214 Section 8 16-Bit Integrated Timer Unit (ITU) • Three additional modes selectable in channels 3 and 4  Reset-synchronized PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of complementary waveforms.  Complementary PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms.
Page 215 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.1 ITU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal clocks: φ, φ/2, φ/4, φ/8 Clock sources External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently General registers GRA0, GRB0 GRA1, GRB1 GRA2, GRB2...
Page 216: Block Diagrams
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.2 Block Diagrams ITU Block Diagram (Overall) Figure 8.1 is a block diagram of the ITU. IMIA0 to IMIA4 TCLKA to TCLKD Clock selector IMIB0 to IMIB4 φ, φ/2, φ/4, φ/8 OVI0 to OVI4 TOCXA , TOCXB Control logic...
Page 217 Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channels 0 and 1 ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA0 IMIB0...
Page 218 Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channel 2 Figure 8.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD TIOCA Clock selector TIOCB φ, φ/2, φ/4, φ/8 Control logic IMIA2...
Page 219 Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagrams of Channels 3 and 4 Figure 8.4 is a block diagram of channel 3. Figure 8.5 is a block diagram of channel 4. TIOCA TCLKA to TIOCB TCLKD Clock selector φ, φ/2, φ/4, φ/8 Control logic IMIA3...
Page 220 Section 8 16-Bit Integrated Timer Unit (ITU) TOCXA TCLKA to TOCXB TCLKD Clock selector φ, φ/2, TIOCA φ/4, φ/8 TIOCB Control logic IMIA4 Comparator IMIB4 OVI4 Module data bus Legend: TCNT4: Timer counter 4 (16 bits) GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) ×...
Page 221: Input/Output Pins
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.3 Input/Output Pins Table 8.2 summarizes the ITU pins. Table 8.2 ITU Pins Abbre- Input/ Channel Name viation Output Function Common Clock input A TCLKA Input External clock A input pin (phase-A input pin in phase counting mode) Clock input B TCLKB...
Page 222 Section 8 16-Bit Integrated Timer Unit (ITU) Abbre- Input/ Channel Name viation Output Function Input capture/output TIOCA Input/ GRA4 output compare or input capture pin compare A4 output PWM output pin in PWM mode, complementary PWM mode, or reset- synchronized PWM mode Input capture/output TIOCB Input/...
Page 223: Register Configuration
Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.4 Register Configuration Table 8.3 summarizes the ITU registers. Table 8.3 ITU Registers Abbre- Initial Channel Address* Name viation Value Common H'FF60 Timer start register TSTR H'E0 H'FF61 Timer synchro register TSNC H'E0 H'FF62 Timer mode register TMDR...
Page 224 Section 8 16-Bit Integrated Timer Unit (ITU) Abbre- Initial Channel Address* Name viation Value H'FF78 Timer control register 2 TCR2 H'80 H'FF79 Timer I/O control register 2 TIOR2 H'88 H'FF7A Timer interrupt enable register 2 TIER2 H'F8 H'FF7B Timer status register 2 TSR2 R/(W)* H'F8...
Page 225 Section 8 16-Bit Integrated Timer Unit (ITU) Abbre- Initial Channel Address* Name viation Value H'FF92 Timer control register 4 TCR4 H'80 H'FF93 Timer I/O control register 4 TIOR4 H'88 H'FF94 Timer interrupt enable register 4 TIER4 H'F8 H'FF95 Timer status register 4 TSR4 R/(W)* H'F8...
Page 226: Register Descriptions
Section 8 16-Bit Integrated Timer Unit (ITU) Register Descriptions 8.2.1 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write...
Page 227 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2). Bit 2 STR2 Description TCNT2 is halted (Initial value) TCNT2 is counting Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 Description...
Page 228: Timer Synchro Register (Tsnc)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. — —...
Page 229 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 Description Channel 2's timer counter (TCNT2) operates independently TCNT2 is preset and cleared independently of other channels (Initial value) Channel 2 operates synchronously TCNT2 can be synchronously preset and cleared...
Page 230: Timer Mode Register (Tmdr)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. —...
Page 231 Section 8 16-Bit Integrated Timer Unit (ITU) In phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in timer control register 2 (TCR2). Phase counting mode takes precedence over these settings. The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase...
Page 232 Section 8 16-Bit Integrated Timer Unit (ITU) When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match with general register B3 (GRB3).
Page 233: Timer Function Control Register (Tfcr)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.4 Timer Function Control Register (TFCR) TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset- synchronized PWM mode, and buffering for channels 3 and 4. — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3...
Page 234 Section 8 16-Bit Integrated Timer Unit (ITU) Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 Bit 4 CMD1 CMD0 Description...
Page 235 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 Description GRB3 operates normally (Initial value) GRB3 is buffered by BRB3 Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3.
Page 236: Timer Output Master Enable Register (Toer)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.5 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. — — EXB4 EXA4 Initial value Read/Write — — Reserved bits Master enable TOCXA , TOCXB...
Page 237 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 3—Master Enable TIOCB (EB3): Enables or disables ITU output at pin TIOCB Bit 3 Description TIOCB output is disabled regardless of TIOR3 and TFCR settings (TIOCB operates as a generic input/output pin). If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
Page 238: Timer Output Control Register (Tocr)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. — —...
Page 239 Section 8 16-Bit Integrated Timer Unit (ITU) Bits 3 and 2—Reserved: These bits cannot be modified and are always read as 1. Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 Description TIOCA...
Page 240: Timer Counters (Tcnt)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.7 Timer Counters (TCNT) TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel. Channel Abbreviation Function TCNT0 Up-counter TCNT1 TCNT2 Phase counting mode: up/down-counter Other modes: up-counter TCNT3 Complementary PWM mode: up/down-counter Other modes: up-counter TCNT4...
Page 241: General Registers (Gra, Grb)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel. Channel Abbreviation Function GRA0, GRB0 Output compare/input capture register GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 Output compare/input capture register;...
Page 242: Buffer Registers (Bra, Brb)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.9 Buffer Registers (BRA, BRB) The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3 and 4. Channel Abbreviation Function BRA3, BRB3 Used for buffering • BRA4, BRB4 When the corresponding GRA or GRB functions as an output compare register, BRA or BRB can function as an output compare...
Page 243: Timer Control Registers (Tcr)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.10 Timer Control Registers (TCR) TCR is an 8-bit register. The ITU has five TCRs, one in each channel. Channel Abbreviation Function TCR0 TCR controls the timer counter. The TCRs in all channels are functionally identical.
Page 244 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 6 Bit 5 CCLR1 CCLR0 Description TCNT is not cleared (Initial value) TCNT is cleared by GRA compare match or input capture* TCNT is cleared by GRB compare match or input capture* Synchronous clear: TCNT is cleared in synchronization with other synchronized timers* Notes: 1.
Page 245: Timer I/O Control Register (Tior)
Section 8 16-Bit Integrated Timer Unit (ITU) When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0.
Page 246 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 7—Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 Bit 5 Bit 4 IOB2 IOB1...
Page 247: Timer Status Register (Tsr)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.12 Timer Status Register (TSR) TSR is an 8-bit register. The ITU has five TSRs, one in each channel. Channel Abbreviation Function TSR0 Indicates input capture, compare match, and overflow status TSR1 TSR2 TSR3 TSR4 —...
Page 248 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow. Bit 2 Description [Clearing condition] (Initial value) Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF* Notes: * TCNT underflow occurs when TCNT operates as an up/down-counter.
Page 249: Timer Interrupt Enable Register (Tier)
Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel Abbreviation Function TIER0 Enables or disables interrupt requests. TIER1 TIER2 TIER3 TIER4 —...
Page 250: Cpu Interface
Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the overflow flag (OVF) in TSR when OVF is set to 1. Bit 2 OVIE Description OVI interrupt requested by OVF is disabled (Initial value) OVI interrupt requested by OVF is enabled Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the...
Page 251 Section 8 16-Bit Integrated Timer Unit (ITU) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8.6 Access to Timer Counter (CPU Writes to TCNT, Word) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8.7 Access to Timer Counter (CPU Reads TCNT, Word) Internal data bus Module Bus interface...
Page 252 Section 8 16-Bit Integrated Timer Unit (ITU) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) Internal data bus Module Bus interface data bus TCNTH TCNTL Figure 8.10 Access to Timer Counter (CPU Reads TCNT, Upper Byte) Internal data bus Module Bus interface...
Page 253: 8-Bit Accessible Registers
Section 8 16-Bit Integrated Timer Unit (ITU) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8.12 and 8.13 show examples of byte read and write access to a TCR. If a word-size data transfer instruction is executed, two byte transfers are performed.
Page 254: Operation
Section 8 16-Bit Integrated Timer Unit (ITU) Operation 8.4.1 Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare.
Page 255 Section 8 16-Bit Integrated Timer Unit (ITU) Buffering: • If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. • If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register.
Page 256: Basic Functions
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.2 Basic Functions Counter Operation When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic.
Page 257 Section 8 16-Bit Integrated Timer Unit (ITU) 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal.
Page 258 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT value Counter cleared by general register compare match H'0000 Time STR bit Figure 8.16 Periodic Counter Operation Count timing: • Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock (φ) or one of three internal clock sources obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Page 259 Section 8 16-Bit Integrated Timer Unit (ITU) φ External clock input TCNT input TCNT N – 1 N + 1 Figure 8.18 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle.
Page 260 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of waveform output: Figure 8.20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B.
Page 261 Section 8 16-Bit Integrated Timer Unit (ITU) Output compare timing: The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB).
Page 262 Section 8 16-Bit Integrated Timer Unit (ITU) Input Capture Function The TCNT value can be captured into a general register when a transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take place on the rising edge, falling edge, or both edges.
Page 263 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of input capture: Figure 8.24 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB. TCNT value Counter cleared by TIOCB input (falling edge)
Page 264 Section 8 16-Bit Integrated Timer Unit (ITU) Input capture signal timing: Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges.
Page 265: Synchronization
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base.
Page 266 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Synchronization Figure 8.27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing.
Page 267: Pwm Mode
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0.
Page 268 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Setup Procedure for PWM Mode Figure 8.28 shows a sample procedure for setting up PWM mode. PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to Select counter clock...
Page 269 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of PWM Mode Figure 8.29 shows examples of operation in PWM mode. The PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB.
Page 270 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%.
Page 271: Reset-Synchronized Pwm Mode
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA...
Page 272 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Setup Procedure for Reset-Synchronized PWM Mode Figure 8.31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted.
Page 273 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Reset-Synchronized PWM Mode Figure 8.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with GRB3, GRA4, GRB4, and TCNT3 respectively, and when the counter is cleared.
Page 274: Complementary Pwm Mode
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA , TIOCB , TIOCA , TOCXA , TIOCB , and...
Page 275 Section 8 16-Bit Integrated Timer Unit (ITU) Setup Procedure for Complementary PWM Mode Figure 8.33 shows a sample procedure for setting up complementary PWM mode. 1. Clear bits STR3 and STR4 to 0 in Complementary PWM mode TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are halted.
Page 276 Section 8 16-Bit Integrated Timer Unit (ITU) Clearing Complementary PWM Mode Figure 8.34 shows a sample procedure for clearing complementary PWM mode. Complementary PWM mode Clear bit CMD1 in TFCR to 0, and set channels 3 and 4 to normal operating Clear complementary mode mode.
Page 277 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of Complementary PWM Mode Figure 8.35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4, and GRB4.
Page 278 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3.
Page 279 Section 8 16-Bit Integrated Timer Unit (ITU) In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ.
Page 280 Section 8 16-Bit Integrated Timer Unit (ITU) Underflow Overflow TCNT4 H'0001 H'0000 H'FFFF H'0000 Flag not set Set to 1 Buffer transfer signal (BR to GR) Buffer transfer No buffer transfer Figure 8.38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs.
Page 281 Section 8 16-Bit Integrated Timer Unit (ITU) GRA3 H'0000 Not allowed Figure 8.39 Changing a General Register Setting by Buffer Transfer (Example 1)  Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a buffer register value outside this range.
Page 282 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT3 TCNT4 T – 1 Illegal changes H'0000 H'FFFF Figure 8.41 Changing a General Register Setting by Buffer Transfer (Caution 2)  General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range.
Page 283: Phase Counting Mode
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2.
Page 284 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Phase Counting Mode Figure 8.44 shows an example of operations in phase counting mode. Table 8.9 lists the up- counting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 285: Buffering
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next.
Page 286 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Buffering Setup Procedure Figure 8.48 shows a sample buffering setup procedure. Buffering Select general register functions Set TIOR to select the output compare or input capture function of the general registers. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR to select buffering of the required general registers.
Page 287 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT value Counter cleared by compare match B H'0250 H'0200 H'0100 H'0000 Time H'0200 H'0100 H'0200 H'0250 H'0200 H'0100 H'0200 Toggle TIOCB output Toggle TIOCA output Compare match A Figure 8.49 Register Buffering (Example 1: Buffering of Output Compare Register) φ...
Page 288 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB.
Page 289 Section 8 16-Bit Integrated Timer Unit (ITU) φ TIOC pin Input capture signal TCNT n + 1 N + 1 Figure 8.52 Input Capture and Buffer Transfer Timing (Example) Rev.3.00 Mar. 26, 2007 Page 267 of 682 REJ09B0353-0300...
Page 290 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows.
Page 291: Itu Output Timing
Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER.
Page 292 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Disabling of ITU Output by External Trigger If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output.
Page 293 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Output Inversion by TOCR The output levels in reset-synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 8.56 shows the timing.
Page 294: Interrupts
Section 8 16-Bit Integrated Timer Unit (ITU) Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR).
Page 295 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Setting of IMFA and IMFB by Input Capture IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 8.58 shows the timing. φ...
Page 296: Clearing Of Status Flags
Section 8 16-Bit Integrated Timer Unit (ITU) φ TCNT H'FFFF H'0000 Overflow signal Figure 8.59 Timing of Setting of OVF 8.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared.
Page 297: Interrupt Sources
Section 8 16-Bit Integrated Timer Unit (ITU) 8.5.3 Interrupt Sources Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1.
Page 298: Usage Notes
Section 8 16-Bit Integrated Timer Unit (ITU) Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear If a counter clear signal occurs in the T state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed.
Page 299 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Word Write and Increment If an increment pulse occurs in the T state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 8.62. TCNT word write cycle φ...
Page 300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Byte Write and Increment If an increment pulse occurs in the T or T state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 8.63, which shows an increment pulse occurring in the T state of a byte write to TCNTH.
Page 301 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Compare Match If a compare match occurs in the T state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8.64. General register write cycle φ...
Page 302 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Write and Overflow or Underflow If an overflow occurs in the T state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1. The same holds for underflow. See figure 8.65. TCNT write cycle φ...
Page 303 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Read and Input Capture If an input capture signal occurs during the T state of a general register read cycle, the value before input capture is read. See figure 8.66. General register read cycle φ...
Page 304 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal.
Page 305 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Input Capture If an input capture signal occurs in the T state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.68. General register write cycle φ...
Page 306 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between Buffer Register Write and Input Capture If a buffer register is used for input capture buffering and an input capture signal occurs in the T state of a write cycle, input capture takes priority and the write to the buffer register is not performed.
Page 307 Section 8 16-Bit Integrated Timer Unit (ITU) Note on Synchronous Preset When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized •...
Page 308 Section 8 16-Bit Integrated Timer Unit (ITU) ITU Operating Modes Table 8.11 (a) ITU Operating Modes (Channel 0) Rev.3.00 Mar. 26, 2007 Page 286 of 682 REJ09B0353-0300...
Page 309 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (b) ITU Operating Modes (Channel 1) Rev.3.00 Mar. 26, 2007 Page 287 of 682 REJ09B0353-0300...
Page 310 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (c) ITU Operating Modes (Channel 2) Rev.3.00 Mar. 26, 2007 Page 288 of 682 REJ09B0353-0300...
Page 311 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (d) ITU Operating Modes (Channel 3) Rev.3.00 Mar. 26, 2007 Page 289 of 682 REJ09B0353-0300...
Page 312 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (e) ITU Operating Modes (Channel 4) Rev.3.00 Mar. 26, 2007 Page 290 of 682 REJ09B0353-0300...
Page 313: Section 9 Programmable Timing Pattern Controller
Section 9 Programmable Timing Pattern Controller Section 9 Programmable Timing Pattern Controller Overview The H8/3039 Group has a built-in programmable timing pattern controller (TPC)* that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently.
Page 314: Block Diagram
Section 9 Programmable Timing Pattern Controller 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the TPC. ITU compare match signals PADDR PBDDR NDERA NDERB Control logic TPMR TPCR Internal data bus Pulse output pins, group 3 NDRB PBDR Pulse output pins, group 2 Pulse output...
Page 315: Tpc Pins
Section 9 Programmable Timing Pattern Controller 9.1.3 TPC Pins Table 9.1 summarizes the TPC output pins. Table 9.1 TPC Pins Name Symbol Function TPC output 0 Output Group 0 pulse output TPC output 1 Output TPC output 2 Output TPC output 3 Output TPC output 4 Output...
Page 316: Registers
Section 9 Programmable Timing Pattern Controller 9.1.4 Registers Table 9.2 summarizes the TPC registers. Table 9.2 TPC Registers Address* Name Abbreviation Initial Value H'FFD1 Port A data direction register PADDR H'00 H'FFD3 Port A data register PADR R/(W)* H'00 H'FFD4 Port B data direction register PBDDR H'00...
Page 317: Register Descriptions
Section 9 Programmable Timing Pattern Controller Register Descriptions 9.2.1 Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR PA DDR...
Page 318: Port B Data Direction Register (Pbddr)
Section 9 Programmable Timing Pattern Controller 9.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value...
Page 319: Next Data Register A (Ndra)
Section 9 Programmable Timing Pattern Controller 9.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP to TP ). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR.
Page 320 Section 9 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 0 and 1 If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7.
Page 321: Next Data Register B (Ndrb)
Section 9 Programmable Timing Pattern Controller 9.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP to TP )*. During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR.
Page 322 Section 9 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 2 and 3 If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3)* is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6.
Page 323: Next Data Enable Register A (Ndera)
Section 9 Programmable Timing Pattern Controller 9.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 to TP ) on a bit-by-bit basis. NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1...
Page 324: Next Data Enable Register B (Nderb)
Section 9 Programmable Timing Pattern Controller 9.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 to TP )* on a bit-by-bit basis. NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9...
Page 325: Tpc Output Control Register (Tpcr)
Section 9 Programmable Timing Pattern Controller 9.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 3 compare match select 1 and 0...
Page 326 Section 9 Programmable Timing Pattern Controller Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP to TP Bit 7 Bit6 G3CMS1 G3CMS0 Description TPC output group 3 (TP to TP...
Page 327 Section 9 Programmable Timing Pattern Controller Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP to TP Bit 3 Bit2 G1CMS1 G1CMS0 Description TPC output group 1 (TP to TP...
Page 328: Tpc Output Mode Register (Tpmr)
Section 9 Programmable Timing Pattern Controller 9.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — —...
Page 329 Section 9 Programmable Timing Pattern Controller Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP to TP Note: * Since this LSI does not have a TP pin, the TP signal cannot be output off-chip. Bit 3 G3NOV Description...
Page 330: Operation
Section 9 Programmable Timing Pattern Controller Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP to TP Bit 0 G0NOV Description Normal TPC output in group 0 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare...
Page 331: Output Timing
Section 9 Programmable Timing Pattern Controller Table 9.3 TPC Operating Conditions NDER Pin Function Generic input port Generic output port Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match.
Page 332: Normal Tpc Output
Section 9 Programmable Timing Pattern Controller 9.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output Figure 9.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set TIOR to make GRA an output compare register (with output inhibited).
Page 333 Section 9 Programmable Timing Pattern Controller Example of Normal TPC Output (Example of Five-Phase Pulse Output) Figure 9.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value Compare match TCNT H'0000 Time NDRA PADR •...
Page 334: Non-Overlapping Tpc Output
Section 9 Programmable Timing Pattern Controller 9.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output Figure 9.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set TIOR to make GRA and GRB output compare registers (with output inhibited).
Page 335 Section 9 Programmable Timing Pattern Controller Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 9.7 shows an example of the use of TPC output for four-phase complementary non- overlapping pulse output. TCNT value TCNT H'0000 Time NDRA PADR Non-overlap margin...
Page 336: Tpc Output Triggering By Input Capture
Section 9 Programmable Timing Pattern Controller 9.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal.
Page 337: Usage Notes
Section 9 Programmable Timing Pattern Controller Usage Notes 9.4.1 Operation of TPC Output Pins to TP * are multiplexed with ITU pin functions. When ITU output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Page 338 Section 9 Programmable Timing Pattern Controller Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC.
Page 339: Section 10 Watchdog Timer
Section 10 Watchdog Timer Section 10 Watchdog Timer 10.1 Overview The H8/3039 Group has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer.
Page 340: Block Diagram
Section 10 Watchdog Timer 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the WDT. Overflow Internal TCNT data bus Read/ Interrupt Interrupt signal write control (interval timer) control TCSR Internal clock sources φ/2 RSTCSR φ/32 φ/64 Reset Reset control Clock φ/128 (internal, external)
Page 341: Register Configuration
Section 10 Watchdog Timer 10.1.4 Register Configuration Table 10.2 summarizes the WDT registers. Table 10.2 WDT Registers Address* Write* Read Name Abbreviation Initial Value H'FFA8 H'FFA8 Timer control/status register TCSR R/(W)* H'18 H'FFA9 Timer counter TCNT H'00 H'FFAA H'FFAB Reset control/status register RSTCSR R/(W)* H'3F...
Page 342: Timer Control/Status Register (Tcsr)
Section 10 Watchdog Timer 10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode and clock source. Note: * TCSR is write-protected by a password. For details see section 10.2.4, Notes on Register Access.
Page 343 Section 10 Watchdog Timer Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value) [Setting condition] Set when TCNT changes from H'FF to H'00...
Page 344: Reset Control/Status Register (Rstcsr)
Section 10 Watchdog Timer Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description φ/2 (Initial value) φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 10.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable* register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal.
Page 345 Section 10 Watchdog Timer Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin* initialize external system devices.
Page 346: Notes On Register Access
Section 10 Watchdog Timer 10.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR These registers must be written by a word transfer instruction.
Page 347 Section 10 Watchdog Timer Writing to RSTCSR RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 10.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte.
Page 348: Operation
Section 10 Watchdog Timer 10.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 10.3.1 Watchdog Timer Operation Figure 10.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR.
Page 349: Interval Timer Operation
Section 10 Watchdog Timer WDT overflow H'FF TME set to 1 TCNT count value H'00 OVF = 1 Start H'00 written Reset H'00 written in TCNT in TCNT Internal reset signal 518 states RESO 132 states Figure 10.4 Watchdog Timer Operation (Mask ROM Version) 10.3.2 Interval Timer Operation Figure 10.5 illustrates interval timer operation.
Page 350: Timing Of Setting Of Overflow Flag (Ovf)
Section 10 Watchdog Timer 10.3.3 Timing of Setting of Overflow Flag (OVF) Figure 10.6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation.
Page 351: Timing Of Setting Of Watchdog Timer Reset Bit (Wrst)
Section 10 Watchdog Timer 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 10.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1.
Page 352: Usage Notes
Section 10 Watchdog Timer 10.5 Usage Notes Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 10.8. Write cycle: CPU writes to TCNT φ...
Page 353: Section 11 Serial Communication Interface
Section 11 Serial Communication Interface Section 11 Serial Communication Interface 11.1 Overview The H8/3039 Group has a serial communication interface (SCI) with two independent channels. The two channels are functionally identical. The SCI can communicate in asynchronous or synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors.
Page 354 Section 11 Serial Communication Interface b. Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format.  Data length: 8 bits ...
Page 355: Block Diagram
Section 11 Serial Communication Interface 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the SCI. Internal data bus Module data bus φ φ/4 Baud rate generator φ/16 Transmit/ receive control φ/64 Parity generation Clock Parity check External clock Legend: RSR: Receive shift register...
Page 356: Input/Output Pins
Section 11 Serial Communication Interface 11.1.3 Input/Output Pins The SCI has the serial pins for each channel as listed in table 11.1. Table 11.1 SCI Pins Channel Name Abbreviation Function Serial clock pin Input/output clock input/output Receive data pin Input receive data input Transmit data pin Output...
Page 357: Register Configuration
Section 11 Serial Communication Interface 11.1.4 Register Configuration The SCI has the internal registers as listed in table 11.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, and control the transmitter and receiver sections. Table 11.2 Registers Channel Address*...
Page 358: Register Descriptions
Section 11 Serial Communication Interface 11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) RSR is an 8-bit register that receives serial data. Read/Write — — — — — — — — The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data.
Page 359: Transmit Shift Register (Tsr)
Section 11 Serial Communication Interface 11.2.3 Transmit Shift Register (TSR) TSR is an 8-bit register used to transmit serial data. Read/Write — — — — — — — — The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
Page 360: Serial Mode Register (Smr)
Section 11 Serial Communication Interface 11.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. STOP CKS1 CKS0 Initial value Read/Write Clock select 1/0 These bits select the baud rate generatorÕs clock source...
Page 361 Section 11 Serial Communication Interface Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 Description 8-bit data (Initial value) 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Page 362 Section 11 Serial Communication Interface Bit 3 STOP Description One stop bit* (Initial value) Two stop bits* Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character. 2. Two stop bits (with value 1) are added at the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting.
Page 363: Serial Control Register (Scr)
Section 11 Serial Communication Interface 11.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1/0...
Page 364 Section 11 Serial Communication Interface Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 Description Transmit-data-empty interrupt request (TXI) is disabled* (Initial value)
Page 365 Section 11 Serial Communication Interface Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 Description Receiving disabled* (Initial value) Receiving enabled* Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values.
Page 366 Section 11 Serial Communication Interface Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE Description Transmit-end interrupt requests (TEI) are disabled* (Initial value) Transmit-end interrupt requests (TEI) are enabled* Note:...
Page 367: Serial Status Register (Ssr)
Section 11 Serial Communication Interface 11.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit transfer...
Page 368 Section 11 Serial Communication Interface SSR is initialized to H'84 by a reset and in standby mode. Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial transmit data can be written in TDR. Bit 7 TDRE Description...
Page 369 Section 11 Serial Communication Interface Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER Description Receiving is in progress or has ended normally (Initial value)* [Clearing conditions] • The chip is reset or enters standby mode •...
Page 370 Section 11 Serial Communication Interface Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 Description Receiving is in progress or has ended normally* (Initial value) [Clearing condition] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0 A receive parity error occurred* [Setting condition]...
Page 371: Bit Rate Register (Brr)
Section 11 Serial Communication Interface Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 Description Multiprocessor bit value in receive data is 0* (Initial value) Multiprocessor bit value in receive data is 1...
Page 372 Section 11 Serial Communication Interface Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode φ φ φ φ (MHz) 2.097152 2.4576 Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 –0.26 0.03 0.16 0.21 0.16 0.16 0.21 0.16 0.16 0.21...
Page 373 Section 11 Serial Communication Interface φ φ φ φ (MHz) 6.144 7.3728 Bit Rate Error Error Error Error (bits/s) –0.44 0.08 –0.07 0.03 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 2400 0.16 0.16 4800 0.16 0.16 9600 –2.34 0.16 19200 –2.34...
Page 374 Section 11 Serial Communication Interface φ φ φ φ (MHz) 14.7456 Bit Rate Error Error Error Error (bits/s) –0.17 0.70 0.03 –0.12 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 1200 0.16 0.16 0.16 2400 0.16 0.16 0.16 4800 0.16 0.16 0.16...
Page 375 Section 11 Serial Communication Interface Table 11.4 Examples of Bit Rates and BRR Settings in Synchronous Mode φ φ φ φ (MHz) Bit Rate (bits/s) — — — — — — — — — — — — — — — —...
Page 376 Section 11 Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n–1 B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 ≤...
Page 377 Section 11 Serial Communication Interface Table 11.5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 11.6 and 11.7 indicate the maximum bit rates with external clock input. Table 11.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings φ...
Page 378 Section 11 Serial Communication Interface Table 11.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000...
Page 379 Section 11 Serial Communication Interface Table 11.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3...
Page 380: Operation
Section 11 Serial Communication Interface 11.3 Operation 11.3.1 Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 11.8.
Page 381 Section 11 Serial Communication Interface Table 11.8 SMR Settings and Serial Communication Formats SMR Settings SCI Communication Format Multi- Stop Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity C/A A A A STOP Mode Length Length Asynchronous 8-bit data...
Page 382: Operation In Asynchronous Mode
Section 11 Serial Communication Interface 11.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible.
Page 383 Section 11 Serial Communication Interface Communication Formats Table 11.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 11.10 Serial Communication Formats (Asynchronous Mode) SMR Settings Serial Communication Format and Frame Length STOP 8-bit data STOP...
Page 384 Section 11 Serial Communication Interface Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR.
Page 385 Section 11 Serial Communication Interface Start of initialization Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after Clear TE and RE bits the setting is made in SCR.
Page 386 Section 11 Serial Communication Interface Transmitting Serial Data (Asynchronous Mode): Figure 11.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, Start transmitting check that the TDRE flag is 1, then write transmit data...
Page 387 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 388 Section 11 Serial Communication Interface Receiving Serial Data (Asynchronous Mode): Figure 11.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3.
Page 389 Section 11 Serial Communication Interface Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR PER = 1? Parity error handling Clear ORER, PER, and FER flags to 0 in SSR Figure 11.7 Sample Flowchart for Receiving Serial Data (2) Rev.3.00 Mar.
Page 390 Section 11 Serial Communication Interface In receiving, the SCI operates as follows. • The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. • Receive data is stored in RSR in order from LSB to MSB. •...
Page 391: Multiprocessor Communication
Section 11 Serial Communication Interface Figure 11.8 shows an example of SCI receive operation in asynchronous mode. Start Parity Stop Start Parity Stop Data Data Idle (mark) state RDRF RXI interrupt handler request reads data in RDR and Framing error, clears RDRF flag to 0 ERI request 1 frame...
Page 392 Section 11 Serial Communication Interface Communication Formats Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11.11. Clock See the description of asynchronous mode. Transmitting processor Serial communication line Receiving Receiving Receiving Receiving processor A...
Page 393 Section 11 Serial Communication Interface Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 11.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the transmit data output function of the TxD pin is selected automatically.
Page 394 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 395 Section 11 Serial Communication Interface Receiving Multiprocessor Serial Data: Figure 11.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving ID receive cycle: set the MPIE bit to 1 in SCR.
Page 396 Section 11 Serial Communication Interface Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit to 0 in SCR Clear ORER and FER flags to 0 in SSR Figure 11.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.3.00 Mar.
Page 397 Section 11 Serial Communication Interface Figure 11.13 shows an example of SCI receive operation using a multiprocessor format. Start Stop Start Stop Data (ID1) Data (data1) Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads Not own ID, so No RXI request, (multiprocessor RDR data and clears...
Page 398: Synchronous Operation
Section 11 Serial Communication Interface 11.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible.
Page 399 Section 11 Serial Communication Interface Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below.
Page 400 Section 11 Serial Communication Interface Transmitting Serial Data (Synchronous Mode): Figure 11.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. SCI initialization: the transmit data output function Initialize of the TxD pin is selected automatically. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit Start transmitting...
Page 401 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. • The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. •...
Page 402 Section 11 Serial Communication Interface Receiving Serial Data (Synchronous Mode): Figure 11.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled.
Page 403 Section 11 Serial Communication Interface Error handling Overrun error handling Clear ORER flag to 0 in SSR Figure 11.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. • The SCI synchronizes with serial clock input or output and initializes internally. •...
Page 404 Section 11 Serial Communication Interface Figure 11.19 shows an example of SCI receive operation. Receive direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt handler request reads data in RDR and request Overrun error,...
Page 405 Section 11 Serial Communication Interface SCI initialization: the transmit data output function of the TxD pin and Initialize receive data input function of the RxD pin are selected, enabling Start transmitting and receiving simultaneous transmitting and receiving. SCI status check and transmit data write: read SSR, check that Read TDRE flag in SSR the TDRE flag is 1, then write...
Page 406: Sci Interrupts
Section 11 Serial Communication Interface 11.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCR.
Page 407: Usage Notes
Section 11 Serial Communication Interface 11.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Page 408 Section 11 Serial Communication Interface Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Page 409 Section 11 Serial Communication Interface 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 11.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). | D –...
Page 410 Section 11 Serial Communication Interface Restrictions in Synchronous Mode When data transmission is performed using an external clock source as the serial clock, an interval of at least 5 states is necessary between clearing the TDRE flag in SSR and the start (falling edge) of the first transmit clock pulse corresponding to each frame (figure 11.22).
Page 411 Section 11 Serial Communication Interface Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI 1. Problem in Operation After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is switched to the port function at the end of transmission, a low-level signal is output for one half-cycle before the port output state is established.
Page 412 Section 11 Serial Communication Interface 2. Usage Note The procedure shown below should be used to prevent low-level output when switching from the SCK pin function to the port function. As this procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit.
Page 413: Section 12 Smart Card Interface
Section 12 Smart Card Interface Section 12 Smart Card Interface 12.1 Overview SCI0 supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.
Page 414: Block Diagram
Section 12 Smart Card Interface 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the Smart Card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate φ/16 generator Transmission/ φ/64 reception control Parity generation Clock Parity check Legend: Smart Card mode register SCMR:...
Page 415: Pin Configuration
Section 12 Smart Card Interface 12.1.3 Pin Configuration Table 12.1 shows the Smart Card interface pin configuration. Table 12.1 Smart Card Interface Pins Pin Name Abbreviation Function Serial clock pin 0 Output clock output Receive data pin 0 Input receive data input Transmit data pin 0 Output transmit data output...
Page 416: Register Descriptions
Section 12 Smart Card Interface 12.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 12.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value Read/Write —...
Page 417 Section 12 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 12.3.4, Register Settings.
Page 418: Serial Status Register (Ssr)
Section 12 Smart Card Interface 12.2.2 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Transmit end Status flag indicating end of transmission Error signal status Status flag indicating that an error signal has been received Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Page 419: Operation
Section 12 Smart Card Interface Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit are as shown below. Bit 2 TEND Description Transmission is in progress...
Page 420: Pin Connections
Section 12 Smart Card Interface 12.3.2 Pin Connections Figure 12.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin.
Page 421: Data Format
Section 12 Smart Card Interface 12.3.3 Data Format Figure 12.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
Page 422 Section 12 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts a date transfer of one frame. The data frame starts with a start bit (Ds, low-level).
Page 423: Register Settings
Section 12 Smart Card Interface 12.3.4 Register Settings Table 12.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below.
Page 424 Section 12 Smart Card Interface SCMR Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.
Page 425: Clock
Section 12 Smart Card Interface 12.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR.
Page 426 Section 12 Smart Card Interface The method of calculating the value from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. φ...
Page 427: Data Transfer Operations
Section 12 Smart Card Interface 12.3.6 Data Transfer Operations Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 428 Section 12 Smart Card Interface Serial Data Transmission As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 12.4 shows an example of the transmission processing flow, and figure 12.5 shows the relation between a transmit operation and the internal registers.
Page 429 Section 12 Smart Card Interface Start Initialization Start transmission ERS = 0? Error processing TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0? Error processing TEND = 1? Clear TE bit to 0 Figure 12.4 Example of Transmission Processing Flow Rev.3.00 Mar.
Page 430 Section 12 Smart Card Interface (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output Data 1 (3) Serial data output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 431 Section 12 Smart Card Interface Start Initialization Start reception ORER = 0 and PER = 0 Error processing RDRF = 1? Read RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit to 0 Figure 12.6 Example of Reception Processing Flow With the above processing, interrupt servicing is possible.
Page 432 Section 12 Smart Card Interface Mode Switching Operation When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed.
Page 433: Usage Note
Section 12 Smart Card Interface 12.4 Usage Note The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In smart card interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate.
Page 434 Section 12 Smart Card Interface Thus the reception margin in smart card interface mode is given by the following formula.  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0)
Page 435 Section 12 Smart Card Interface Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 12.8 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
Page 436 Section 12 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 12.9 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1.
Page 437: Section 13 A/D Converter
Section 13 A/D Converter Section 13 A/D Converter 13.1 Overview The H8/3039 Group includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 17.6, Module Standby Function.
Page 438: Block Diagram
Section 13 A/D Converter 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the A/D converter. Internal Module data bus data bus 10-bit D/A – φ/8 Comparator Analog Control circuit multi- plexer Sample-and- φ/16 hold circuit interrupt ADTRG Legend: ADCR: A/D control register ADCSR:...
Page 439: Input Pins
Section 13 A/D Converter 13.1.3 Input Pins Table 13.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN to AN ), and group 1 (AN to AN ). AV and AV are the power supply for the analog circuits in the A/D converter.
Page 440: Register Configuration
Section 13 A/D Converter 13.1.4 Register Configuration Table 13.2 summarizes the A/D converter's registers. Table 13.2 A/D Converter Registers Address* Name Abbreviation Initial Value H'FFE0 A/D data register A (high) ADDRAH H'00 H'FFE1 A/D data register A (low) ADDRAL H'00 H'FFE2 A/D data register B (high) ADDRBH...
Page 441: Register Descriptions
Section 13 A/D Converter 13.2 Register Descriptions 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) — — — — — — ADDRn Initial value Read/Write (n = A to D) A/D conversion data Reserved bits 10-bit data giving an A/D conversion result The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion.
Page 442: A/D Control/Status Register (Adcsr)
Section 13 A/D Converter 13.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value R/(W) * Read/Write Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable...
Page 443 Section 13 A/D Converter Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE Description A/D end interrupt request (ADI) is disabled (Initial value) A/D end interrupt request (ADI) is enabled Bit 5—A/D Start (ADST): Starts or stops A/D conversion.
Page 444: A/D Control Register (Adcr)
Section 13 A/D Converter Group Selection Channel Selection Description Single Mode Scan Mode (Initial value) , AN to AN to AN , AN to AN to AN 13.2.3 A/D Control Register (ADCR) TRGE — — — — — — — Initial value Read/Write —...
Page 445: Cpu Interface
Section 13 A/D Converter 13.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP).
Page 446: Operation
Section 13 A/D Converter 13.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 13.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input.
Page 447 Section 13 A/D Converter Figure 13.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev.3.00 Mar. 26, 2007 Page 425 of 682 REJ09B0353-0300...
Page 448: Scan Mode (Scan = 1)
Section 13 A/D Converter 13.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN when CH2 = 0, AN when CH2 = 1).
Page 449 Section 13 A/D Converter Figure 13.4 Example of A/D Converter Operation (Scan Mode, Channels AN to AN Selected) Rev.3.00 Mar. 26, 2007 Page 427 of 682 REJ09B0353-0300...
Page 450: Input Sampling And A/D Conversion Time
Section 13 A/D Converter 13.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 13.5 shows the A/D conversion timing.
Page 451: External Trigger Input Timing
Section 13 A/D Converter Table 13.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Synchronization delay — — Input sampling time — — — — A/D conversion time — — CONV Note: Values in the table are numbers of states. 13.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
Page 452: Interrupts
Section 13 A/D Converter 13.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 13.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins (1) Analog input voltage range The voltage applied to analog input pins AN...
Page 453 Section 13 A/D Converter If a filter capacitor is connected as shown in figure 13.7, the input currents at the analog input pins to AN ) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance ), an error will arise in the analog input pin voltage.
Page 454 Section 13 A/D Converter 10 kΩ To A/D converter 20 pF Note: Values are reference values. Figure 13.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions H8/3039 Group A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes •...
Page 455 Section 13 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 13.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 13.10 A/D Conversion Precision Definitions (2) Rev.3.00 Mar.
Page 456 Section 13 A/D Converter Permissible Signal Source Impedance H8/3039 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 457: Section 14 Ram
Section 14 RAM Section 14 RAM 14.1 Overview The H8/3039 has 4 kbytes of on-chip static RAM, H8/3038 has 2 kbytes, H8/3037 has 1 kbyte, and H8/3036 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer.
Page 458: Block Diagram
Section 14 RAM 14.1.1 Block Diagram Figure 14.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Bus interface SYSCR H'FEF10 * H'FEF11 * H'FEF12 * H'FEF13 * On-chip RAM H'FFF0E * H'FFF0F * Even addresses...
Page 459: System Control Register (Syscr)
Section 14 RAM 14.2 System Control Register (SYSCR) SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable bit Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM.
Page 460: Operation
Section 14 RAM 14.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip RAM when addressing the addresses shown in table 14.1 in each operation mode. When the RAME bit is cleared to 0 in modes 1, 3, and 5 (expanded modes), external address space is accessed.
Page 461: Section 15 Rom
Section 15 ROM Section 15 ROM 15.1 Overview The H8/3039 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8/3038 has 64 kbytes, the H8/3037 has 32 kbytes and H8/3036 has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus.
Page 462: Overview Of Flash Memory
Section 15 ROM 15.2 Overview of Flash Memory 15.2.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time.
Page 463: Block Diagram
Section 15 ROM 15.2.2 Block Diagram Figure 15.1 shows a block diagram of the flash memory. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR * EBR * FWE pin * Operating Bus interface/controller mode Mode pins RAMCR * FLMSR * H'00000...
Page 464: Pin Configuration
Section 15 ROM 15.2.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 15.2. Table 15.2 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable FWE* Input Flash program/erase protection by hardware Mode 2 Input Sets this LSI operating mode...
Page 465: Register Descriptions
Section 15 ROM 15.3 Register Descriptions 15.3.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit.
Page 466 Section 15 ROM Modes Initial value 1 to 4, Read/Write and 6 Modes Initial value 5 and 7 Read/Write Program mode Designates transition to or exit from program mode Erase mode Designates transition to or exit from erase mode Program-verify mode Designates transition to or exit from program-verify mode...
Page 467 Section 15 ROM Bit 6—Software Write Enable Bit (SWE)* : This bit enables/disables flash memory programming/erasing. This bit should be set before setting FLMCR bits 5 to 0, and EBR bits 7 to 0. Do not set the ESU, PSU, EV, PV, E, or P bits at the same time. Bit 6 Description Program/erase disabled...
Page 468 Section 15 ROM Bit 3—Erase-Verify (EV)* : Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When FWE = 1, and SWE = 1 Bit 2—Program-Verify (PV)*...
Page 469: Erase Block Register (Ebr)
Section 15 ROM Bit 0—Program (P)* : Selects program mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time. Bit 0 Description Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Notes: 1.
Page 470 Section 15 ROM Modes Initial value 1 to 4, Read/Write and 6 Initial value Modes 5 and 7 Read/Write Bits 7 to 0—Block 7 to 0 (EB7 to EB0): These bits select blocks (EB7 to EB0) to be erased. Bits 7 to 0 EB7 to EB0 Description Block EB7 to EB0 is not selected.
Page 471: Ram Control Register (Ramcr)
Section 15 ROM 15.3.3 RAM Control Register (RAMCR) RAMCR selects the RAM area used when emulating real-time reprogramming of the flash memory. — — — — RAMS RAM2 RAM1 — Initial value Modes Read/Write 1 to 4 — — — —...
Page 472 Section 15 ROM Bit 0—Reserved: This bit cannot be modified and is always read as 1. Note: * Flash memory emulation by RAM is not supported for Mode 6 (single chip normal mode), so programming is possible, but do not set 1. When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to 1.
Page 473: Flash Memory Status Register (Flmsr)
Section 15 ROM 15.3.4 Flash Memory Status Register (FLMSR) The flash memory status register (FLMSR) detects flash memory errors. FLER — — — — — — — Initial value Read/Write — — — — — — — Reserved bits Flash memory error Status flag indicating that an error was detected during programming or erasing...
Page 474: On-Board Programming Modes
Section 15 ROM 15.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 15.6.
Page 475 Section 15 ROM On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The flash memory is in the erased state when the When boot mode is entered, the boot program in device is shipped. The description here applies to this chip (originally incorporated in the chip) is the case where the old program version or data started, an SCI communication check is carried...
Page 476 Section 15 ROM • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the When the FWE pin is driven high, user software programming/ erase control program to on-chip confirms this fact, executes the transfer program RAM should be written into the flash memory by in the flash memory, and transfers the the user beforehand.
Page 477: Boot Mode
Section 15 ROM 15.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. In reset start, after setting this LSI pin to the boot mode, start the microcomputer boot program, measure the Low period of the data sent from the host, and select the bit rate register (BRR) value beforehand.
Page 478 Section 15 ROM Start Set pins to boot program mode Set this LSI to the boot mode and reset starts the LSI. and execute reset-start Set the host to the prescribed bit rate (4800, 9600) Host transfers data (H'00) and consecutively send H'00 data in 8-bit data, continuously at prescribed bit rate 1 stop bit format.
Page 479 Section 15 ROM Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 15.7 Measuring the Low Period of the Communication Data from the Host When boot mode is initiated, this LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host (figure 15.7).
Page 480 Section 15 ROM On-Chip RAM Area Divisions in Boot Mode In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 15.8. The boot program area can be used when a transition is made to the execution state for the user program transferred to RAM.
Page 481 Section 15 ROM (4) The RXD and TXD pins should be pulled up on the board. (5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing the RE and TE bits in serial control register (SCR)) before branching to the user program. However, the adjusted bit rate is held in the bit rate register (BRR).
Page 482: User Program Mode
Section 15 ROM 3. See section 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory Programming/Erasing. With the mask ROM version of the H8/3039, H8/3038, H8/3037, and H8/3036, the minimum reset period during operation is 10 system clocks. However, the flash memory versions of the H8/3039 requires a minimum of 20 system clocks.
Page 483 Section 15 ROM <Procedure> − MD The user writes a program that executes steps 3 to 8 in advance = 101, 111 as shown below . Sets the mode pin to an on-chip ROM enable mode (mode 5 or 7). Reset start Starts the CPU via reset.
Page 484: Programming/Erasing Flash Memory
Section 15 ROM 15.5 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR.
Page 485: Program Mode
Section 15 ROM E = 1 Erase setup state Erase mode E = 0 Normal mode FWE = 1 FWE = 0 Erase-verify mode On-board SWE = 1 Software programming mode reprogramming software reprogramming enable state disable state SWE = 0 P = 1 Program setup state Programming mode...
Page 486: Program-Verify Mode
Section 15 ROM Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (y + z + α + ß) µs as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR. The operating mode is then switched to program mode by setting the P bit in FLMCR after the elapse of at least (y) µs.
Page 487 Section 15 ROM Start Set SWE bit in FLMCR Wait (x) µs Store 32-byte write data in write data area and reprogram data area Programming operation counter n ← 1 Notes: 1. Programming should be performed in the erased state. Consecutively write 32-byte data in (Perform 32-byte programming on memory after all 32 bytes reprogram data area in RAM to flash memory...
Page 488: Erase Mode
Section 15 ROM 15.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 15.12. For the wait time (x, y, z, α, β, γ, ε, η) after setting or clearing of each bit in the flash memory control register (FLMCR) and the maximum erase count (N), see table 18.15.
Page 489 Section 15 ROM Start Set SWE bit in FLMCR Wait (x) µs Erase counter n ← 1 Set EBR Enable WDT Set ESU bit in FLMCR Wait (y) µs Set E bit in FLMCR Start of erase Wait (z) ms Clear E bit in FLMCR End of erase Wait (α) µs...
Page 490: Flash Memory Protection
Section 15 ROM 15.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 15.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted.
Page 491 Section 15 ROM Table 15.8 Hardware Protection Function Item Description Program Erase Verify* • FWE pin When a low level is input to the FWE protection pin, FLMCR and EBR are initialized, and the program/erase-protected state is entered.* • Reset/standby In a reset (including a WDT overflow protection reset) and in standby mode, FLMCR...
Page 492: Software Protection
Section 15 ROM 15.6.2 Software Protection Software protection can be implemented by setting the RAMS bit in RAM control register (RAMCR) and erase block register (EBR). When software protection is in effect, setting the P or E bit in flash memory control register (FLMCR) does not cause a transition to program mode or erase mode.
Page 493: Error Protection
Section 15 ROM 15.6.3 Error Protection In error protection, an error is detected when this LSI runaway occurs during flash memory programming/erasing* , or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Page 494 Section 15 ROM Memory read verify mode RD VF PR ER FLER = 0 P=1 or E=1 P = 0 and E = 0 Reset or standby mode Program mode (hardware protection) Erase mode Reset or hardware standby mode RD VF PR ER INIT FLER = 0 RD VF PR ER FLER = 0 Error occurrence Reset or hardware...
Page 495: Nmi Input Disable Conditions
Section 15 ROM programming and erasing. In such cases, always forcibly return (reprogram) by boot mode. However, overprogramming and overerasing may prevent the boot mode from starting normally. 15.6.4 NMI Input Disable Conditions While flash memory is being programmed/erased and the boot program is executing in the boot mode (however, period up to branching to on-chip RAM area)* , NMI input is disabled because the programming/erasing operations have priority.
Page 496: Flash Memory Emulation By Ram
Section 15 ROM 15.7 Flash Memory Emulation by RAM Erasing and programming the flash memory takes time, which can make it difficult to tune parameters and other data in real time. In this case, overlapping part (H'FF800 to H'FFBFF) of RAM onto a small block area of flash memory can be performed to emulate real-time reprogramming of flash memory.
Page 497: Flash Memory Prom Mode
This LSI has a PROM mode, besides an on-board programming mode, as a flash memory program/erase mode. In the PROM mode, a program can be freely written to the on-chip ROM using a PROM programmer that supports the Renesas Technology 128 kbytes flash memory on- chip microcomputer device type.
Page 498: Memory Map
Section 15 ROM 15.8.2 Memory Map Figure 15.15 shows the PROM mode memory map. Address in Address in This LSI MCU mode PROM mode H'00000 H'00000 On-chip ROM area H'1FFFF H'1FFFF Figure 15.15 PROM Mode Memory Map 15.8.3 PROM Mode Operation Table 15.10 shows how the different operating modes are set when using PROM mode, and table 15.11 lists the commands used in PROM mode.
Page 499 Section 15 ROM Table 15.10 Settings for Each Operating Mode in PROM Mode Pin Names* Mode to D to A Read or 0 Data output Output disable or 0 Hi-Z Command write or 0 Data input Ain* Chip disable* or 0 Hi-Z Legend: Low level...
Page 500 Section 15 ROM Table 15.12 DC Characteristics in Memory Read Mode Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Test Conditions Input high –0 –A — Vcc +0.3 voltage Input low –0 –A —...
Page 501: Memory Read Mode
Section 15 ROM 15.8.4 Memory Read Mode AC Characteristics Table 15.13 AC Characteristics in Memory Read Mode Transition Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time...
Page 502 Section 15 ROM Table 15.14 AC Characteristics in Memory Contents Read Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Access time — µs CE output delay time — OE output delay time —...
Page 503 Section 15 ROM Table 15.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 504: Auto-Program Mode
Section 15 ROM 15.8.5 Auto-Program Mode AC Characteristics Table 15.16 AC Characteristics in Auto-Program Mode Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 505 Section 15 ROM Address stable A16–A0 nxtc nxtc wsts Data transfer 1byte to 128bytes write I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'00 H'40 I/O5–I/O0 Figure 15.20 Auto-Program Mode Timing Waveforms Cautions on Use of Auto-Program Mode •...
Page 506: Auto-Erase Mode
Section 15 ROM 15.8.6 Auto-Erase Mode AC Characteristics Table 15.17 AC Characteristics in Auto-Erase Mode Conditions: V = 5.0 V ±10%, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs nxtc CE hold time —...
Page 507: Status Read Mode
Section 15 ROM Caution on Use of Erase-Program Mode • Auto-erase mode supports only entire memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O 6. Alternatively, status read mode can also be used for this purpose.
Page 508 Section 15 ROM A16–A0 nxtc nxtc nxtc I/O7–I/O0 H'71 H'71 Note: I/O3 and I/O2 are undefined. Figure 15.22 Status Read Mode Timing Waveforms Table 15.19 Status Read Mode Return Commands Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Attribute Normal Command...
Page 509: Prom Mode Transition Time
Section 15 ROM 15.8.8 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 15.20 Stipulated Transition Times to Command Wait State Item Symbol Unit...
Page 510: Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 511 Section 15 ROM (2) Notes on powering on/powering off (See figures 15.25 to 15.27.) Input a high level to the FWE pin after verifying Vcc. Before turning off Vcc, set the FWE pin to a low level. When powering on and powering off the Vcc power supply, fix the FWE pin a low level and set the flash memory to the hardware protection mode.
Page 512 Section 15 ROM • Apply an input to FWE when the program is not running away. When applying an input to the FWE pin, the program execution state must be supervised using a watchdog timer, etc. • Input low level to the FWE pin when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR have been cleared.
Page 513 Section 15 ROM (9) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10) Do not touch the socket adapter or chip during programming.
Page 514 Section 15 ROM Wait Programming and time: x erase possible φ Min 0 µs OSC1 to MD clear SWE bit : Flash memory access disabled period (x: Wait time after SWE setting) * : Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1.
Page 515 Section 15 ROM Programming Programming Wait Programming and Wait erase Wait Programming and Wait erase time: x erase possible time: x possible time: x erase possible time: x possible φ OSC1 Min 0 µs to MD RESW SWE set SWE clear SWE bit Boot mode Mode...
Page 516: Mask Rom Overview
Section 15 ROM 15.10 Mask ROM Overview 15.10.1 Block Diagram Figure 15.28 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'00000 H'00001 H'00002 H'00003 On-chip ROM H'1FFFE H'1FFFF Even addresses Odd addresses Figure 15.28 ROM Block Diagram (H8/3039) Rev.3.00 Mar.
Page 517: Notes On Ordering Mask Rom Version Chip
Section 15 ROM 15.11 Notes on Ordering Mask ROM Version Chip When ordering the H8/3039 Group chips with a mask ROM, note the following. • When ordering through an EPROM, use a 128-kbyte one. • Fill all the unused addresses with H'FF as shown in figure15.29 to make the ROM data size 128 kbytes for all H8/3039 Group chips, which incorporate different sizes of ROM.
Page 518 Section 15 ROM Rev.3.00 Mar. 26, 2007 Page 496 of 682 REJ09B0353-0300...
Page 519: Section 16 Clock Pulse Generator
Section 16 Clock Pulse Generator Section 16 Clock Pulse Generator 16.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock frequency to generate the system clock (φ).
Page 520: Block Diagram
Section 16 Clock Pulse Generator 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the clock pulse generator. XTAL Duty Frequency adjustment Oscillator Prescalers divider circuit EXTAL Division control register φ φ/2 to φ/4096 Data bus Figure 16.1 Block Diagram of Clock Pulse Generator 16.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock...
Page 521: Connecting A Crystal Resonator
Section 16 Clock Pulse Generator 16.2.1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as in the example in figure 16.2. The damping resistance Rd should be selected according to table 16.1. An AT-cut parallel-resonance crystal should be used. EXTAL XTAL = 10 pF to 22 pF...
Page 522 Section 16 Clock Pulse Generator Table 16.2 Crystal Resonator Parameters Frequency (MHz) 2 Rs max (Ω Ω Ω Ω ) Co max (pF) Use a crystal resonator with a frequency equal to the system clock frequency (φ). Notes on Board Design When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation.
Page 523: External Clock Input
Section 16 Clock Pulse Generator 16.2.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 16.5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. EXTAL External clock input XTAL...
Page 524 Section 16 Clock Pulse Generator External Clock The external clock frequency should be equal to the system clock frequency (φ). Table 16.3 and figure 16.6 indicate the clock timing. Table 16.3 Clock Timing 2.7 V to 5.5 V 5.0 V ±10% Item Symbol Min Unit...
Page 525 Section 16 Clock Pulse Generator Table 16.4 and figure 16.7 show the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t ).
Page 526: Duty Adjustment Circuit
Section 16 Clock Pulse Generator 16.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 16.4 Prescalers The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
Page 527: Division Control Register (Divcr)
Section 16 Clock Pulse Generator 16.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. — — — — — — DIV1 DIV0 Initial value Read/Write — — — — —...
Page 528: Usage Notes
Section 16 Clock Pulse Generator 16.5.3 Usage Notes The DIVCR setting changes the φ frequency, so note the following points. • Select a frequency division ratio that stays within the assured operation range specified for the in the AC electrical characteristics. Note that φ clock cycle time t = 1 MHz.
Page 529: Section 17 Power-Down State
Section 17 Power-Down State Section 17 Power-Down State 17.1 Overview This LSI has a power-down state that greatly reduces power consumption by halting CPU functions, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: •...
Page 530 Section 17 Power-Down State Table 17.1 Power-Down State and Module Standby Function Rev.3.00 Mar. 26, 2007 Page 508 of 682 REJ09B0353-0300...
Page 531: Register Configuration
Section 17 Power-Down State 17.2 Register Configuration This LSI has a system control register (SYSCR) that controls the power-down state, and a module standby control register (MSTCR) that controls the module standby function. Table 17.2 summarizes this register. Table 17.2 Register Configuration Address* Name Abbreviation...
Page 532 Section 17 Power-Down State Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY Description...
Page 533: Module Standby Control Register (Mstcr)
Section 17 Power-Down State 17.2.2 Module Standby Control Register (MSTCR) MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter modules.
Page 534 Section 17 Power-Down State Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby. Bit 4 MSTOP4 Description SCI0 operates normally (Initial value) SCI0 is in standby state Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby. Bit 3 MSTOP3 Description...
Page 535: Sleep Mode
Section 17 Power-Down State 17.3 Sleep Mode 17.3.1 Transition to Sleep Mode When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained.
Page 536: Software Standby Mode
Section 17 Power-Down State 17.4 Software Standby Mode 17.4.1 Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt.
Page 537: Selection Of Oscillator Waiting Time After Exit From Software Standby Mode
Section 17 Power-Down State 17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR, and its DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator Set STS2 to STS0, and DIV1 and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms.
Page 538: Sample Application Of Software Standby Mode
Section 17 Power-Down State 17.4.4 Sample Application of Software Standby Mode Figure 17.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs.
Page 539: Hardware Standby Mode
Section 17 Power-Down State 17.5 Hardware Standby Mode 17.5.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU and on-chip supporting modules.
Page 540: Timing For Hardware Standby Mode
Section 17 Power-Down State 17.5.3 Timing for Hardware Standby Mode Figure 17.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high.
Page 541: Module Standby Function
Section 17 Power-Down State 17.6 Module Standby Function 17.6.1 Module Standby Timing The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0, SCI1, and A/D converter) independently of the power-down state. This standby function is controlled by bits MSTOP5 to MSTOP3 and MSTOP0 in MSTCR.
Page 542: System Clock Output Disabling Function
Section 17 Power-Down State 17.7 System Clock Output Disabling Function Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP bit is set to 1, output of the system clock halts and the φ pin is placed in the high-impedance state. Figure 17.3 shows the timing of the stopping and starting of system clock output.
Page 543: Section 18 Electrical Characteristics
Section 18 Electrical Characteristics Section 18 Electrical Characteristics 18.1 Electrical Characteristics of Mask ROM Version 18.1.1 Absolute Maximum Ratings Table 18.1 lists the absolute maximum ratings. Table 18.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 7)* –0.3 to V +0.3...
Page 544: Dc Characteristics
Section 18 Electrical Characteristics 18.1.2 DC Characteristics Table 18.2 lists the DC characteristics. Table 18.3 lists the permissible output currents. Table 18.2 DC Characteristics (1) Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 545 Section 18 Electrical Characteristics Item Symbol Unit Test Conditions STBY, NMI, Input — — µA = 0.5 to RES, MD leakage , MD –0.5 V current Port 7 — — µA = 0.5 to –0.5 V Three-state Ports 1, 2, 3, 5, —...
Page 546 Section 18 Electrical Characteristics Table 18.2 DC Characteristics (2) Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 547 Section 18 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1, 2, 3, 5, — — µA = 0.5 V to leakage 6, 8, 9, A, B –0.5 V current RESO — — 10.0 µA (off state) Input Ports 2, 5 –I —...
Page 548 Section 18 Electrical Characteristics Table 18.2 DC Characteristics (3) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit Test Conditions...
Page 549 Section 18 Electrical Characteristics Item Symbol Unit Test Conditions Three-state Ports 1, 2, 3, 5, — — µA = 0.5 V to leakage 6, 8 to B –0.5 V current RESO — — 10.0 µA (off state) Input Ports 2, 5 –I —...
Page 550 Section 18 Electrical Characteristics Table 18.3 Permissible Output Currents Conditions: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 551 Section 18 Electrical Characteristics 2 kΩ Port Darlington pair Figure 18.1 Darlington Pair Drive Circuit (Example) Ports 600 Ω Figure 18.2 LED Drive Circuit (Example) Rev.3.00 Mar. 26, 2007 Page 529 of 682 REJ09B0353-0300...
Page 552: Ac Characteristics
Section 18 Electrical Characteristics 18.1.3 AC Characteristics Bus timing parameters are listed in table 18.4. Control signal timing parameters are listed in table 18.5. Timing parameters of the on-chip supporting modules are listed in table 18.6. Table 18.4 Bus Timing = 0 V, φ...
Page 553 Section 18 Electrical Characteristics Condition A Condition B Condition C 8 MHz 10 MHz 18 MHz Test Item Symbol Unit Conditions Write data delay time — — — Figure 18.7, Figure 18.8 Write data setup time 1 — — — WDS1 Write data setup time 2 —...
Page 554 Section 18 Electrical Characteristics Table 18.5 Control Signal Timing = 0 V, φ = 2 MHz to Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) = 0 V, φ...
Page 555 Section 18 Electrical Characteristics Table 18.6 Timing of On-Chip Supporting Modules = 0 V, φ = 2 MHz to Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV 8 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications)
Page 556 Section 18 Electrical Characteristics Condition A Condition B Condition C 8 MHz 10 MHz 18 MHz Test Item Symbol Unit Conditions Transmit data delay — — — Figure 18.18 time Receive data setup — — — time (synchronous) Receive data hold —...
Page 557: A/D Conversion Characteristics
Section 18 Electrical Characteristics 18.1.4 A/D Conversion Characteristics Table 18.7 lists the A/D conversion characteristics. Table 18.7 A/D Converter Characteristics = 0 V, φ = 2 MHz to Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV 8 MHz, T = –20°C to +75°C (regular specifications), T...
Page 558: Electrical Characteristics Of Flash Memory Version
Section 18 Electrical Characteristics 18.2 Electrical Characteristics of Flash Memory Version 18.2.1 Absolute Maximum Ratings Table 18.8 lists the absolute maximum ratings. Table 18.8 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 7)* –0.3 to V +0.3 Input voltage (port 7)
Page 559: Dc Characteristics
Section 18 Electrical Characteristics 18.2.2 DC Characteristics Table 18.9 lists the DC characteristics. Table 18.10 lists the permissible output currents. Table 18.9 DC Characteristics (1) Conditions: V = 5.0 V ±10%, AV = 5.0 V ±10%, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 560 Section 18 Electrical Characteristics Item Symbol Unit Test Conditions STBY, NMI, Input — — µA = 0.5 V to RES, MD leakage , MD –0.5 V current Port 7 — — µA = 0.5 V to –0.5 V — — Three-state Ports 1, 2, 3, —...
Page 561 Section 18 Electrical Characteristics Table 18.9 DC Characteristics (2) Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) (Programming/Erasing Conditions: V = 3.0 V to 3.6 V, T = 0°C to +75°C (regular...
Page 562 Section 18 Electrical Characteristics Item Symbol Unit Test Conditions STBY, NMI, Input — — µA = 0.5 V to RES, MD leakage –0.5 V current , MD Port 7 — — µA = 0.5 V to –0.5 V — — µA = 0.5 V to –0.5 V...
Page 563 Section 18 Electrical Characteristics Table 18.10 Permissible Output Currents Conditions: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol Unit...
Page 564 Section 18 Electrical Characteristics 2 kΩ Port Darlington pair Figure 18.4 Darlington Pair Drive Circuit (Example) Ports 600 Ω Figure 18.5 LED Drive Circuit (Example) Rev.3.00 Mar. 26, 2007 Page 542 of 682 REJ09B0353-0300...
Page 565: Ac Characteristics
Section 18 Electrical Characteristics 18.2.3 AC Characteristics Bus timing parameters are listed in table 18.11. Control signal timing parameters are listed in table 18.12. Timing parameters of the on-chip supporting modules are listed in table 18.13. Table 18.11 Bus Timing = 0 V, φ...
Page 566 Section 18 Electrical Characteristics Condition A Condition B 10 MHz 18 MHz Test Item Symbol Unit Conditions Write data delay time — — Figure 18.7, Figure 18.8 Write data setup time 1 — — WDS1 Write data setup time 2 –10 —...
Page 567 Section 18 Electrical Characteristics Table 18.12 Control Signal Timing = 0 V, φ = 2 to 10 MHz, Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) = 0 V, φ...
Page 568 Section 18 Electrical Characteristics Table 18.13 Timing of On-Chip Supporting Modules = 0 V, φ = 2 MHz to Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV 10 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications)
Page 569 Section 18 Electrical Characteristics Condition A Condition B 10 MHz 18 MHz Test Item Symbol Unit Conditions Ports Output data delay time — — Figure 18.14 Input data setup time — — Input data hold time — — C = 90 pF: ports 1, 2, 3, 5, 6, 8, φ This LSI C = 30 pF: ports 9, A, B output pin...
Page 570: A/D Conversion Characteristics
Section 18 Electrical Characteristics 18.2.4 A/D Conversion Characteristics Table 18.14 lists the A/D conversion characteristics. Table 18.14 A/D Converter Characteristics = 0 V, φ = 2 MHz to Condition A: V = 3.0 V to 5.5 V, AV = 3.0 V to 5.5 V, V = AV 10 MHz, T = –20°C to +75°C (regular specifications), T...
Page 571: Flash Memory Characteristics
Section 18 Electrical Characteristics 18.2.5 Flash Memory Characteristics Table 18.15 shows the flash memory characteristics. Table 18.15 Flash Memory Characteristics (1) Conditions: V = 4.5 V to 5.5 V, AV = 4.5 V to 5.5 V, V = AV = 0 V = 0°C to +75°C (program/erase operating temperature range: regular specifications), T = 0°C to +85°C (program/erase operating temperature range:...
Page 572 Section 18 Electrical Characteristics 3. Block erase time (Shows the period the E bit in FLMCR is set. It does not include the erase verification time.) 4. To specify the maximum programming time (t P (max)) in the 32-byte programming flowchart, set the max value (403) for the maximum programming count (N).
Page 573 Section 18 Electrical Characteristics Table 18.15 Flash Memory Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = AV = 0 V = 0°C to +75°C (Programming/erasing operating temperature range: regular specification) T = 0°C to +85°C (Programming/erasing operating temperature range: wide-range specification)
Page 574: Operational Timing
Section 18 Electrical Characteristics 4. To specify the maximum programming time (t (max)) in the 32-byte programming flowchart, set the maximum value (403) for the maximum programming count (N). The wait time after P bit setting (z) should be changed as follows according to the programming counter value.
Page 575 Section 18 Electrical Characteristics φ to A ACC3 ACC3 (read) ACC1 to D (read) WR (write) WSW1 WDS1 to D (write) Figure 18.7 Basic Bus Cycle: Two-State Access Rev.3.00 Mar. 26, 2007 Page 553 of 682 REJ09B0353-0300...
Page 576 Section 18 Electrical Characteristics φ to A ACC4 ACC4 RD (read) ACC2 to D (read) WSW2 WR (write) WDS2 to D (write) Figure 18.8 Basic Bus Cycle: Three-State Access Rev.3.00 Mar. 26, 2007 Page 554 of 682 REJ09B0353-0300...
Page 577 Section 18 Electrical Characteristics φ to A RD (read) to D (read) WR (write) to D (write) WAIT Figure 18.9 Basic Bus Cycle: Three-State Access with One Wait State Rev.3.00 Mar. 26, 2007 Page 555 of 682 REJ09B0353-0300...
Page 578: Control Signal Timing
Section 18 Electrical Characteristics 18.3.2 Control Signal Timing Control signal timing is shown as follows: • Reset input timing Figure 18.10 shows the reset input timing. • Reset output timing Figure 18.11 shows the reset output timing. • Interrupt input timing Figure 18.12 shows the interrupt input timing for NMI and IRQ , IRQ , IRQ...
Page 579 Section 18 Electrical Characteristics φ NMIS NMIH NMIS NMIH NMIS IRQ : Edge-sensitive IRQ : Level-sensitive IRQ (i = 0, 1, 4, and 5) NMIW (j = 0, 1) Figure 18.12 Interrupt Input Timing Rev.3.00 Mar. 26, 2007 Page 557 of 682 REJ09B0353-0300...
Page 580: Clock Timing
Section 18 Electrical Characteristics 18.3.3 Clock Timing Clock timing is shown below. • Oscillator settling timing Figure 18.13 shows the oscillator settling timing. φ STBY OSC1 OSC1 Figure 18.13 Oscillator Settling Timing 18.3.4 TPC and I/O Port Timing TPC and I/O port timing is shown below. φ...
Page 581: Itu Timing
Section 18 Electrical Characteristics 18.3.5 ITU Timing ITU timing is shown as follows: • ITU input/output timing Figure 18.15 shows the ITU input/output timing. • ITU external clock input timing Figure 18.16 shows the ITU external clock input timing. φ TOCD Output compare *...
Page 582: Sci Input/Output Timing
Section 18 Electrical Characteristics 18.3.6 SCI Input/Output Timing SCI timing is shown as follows: • SCI input clock timing Figure 18.17 shows the SCI input clock timing. • SCI input/output timing (synchronous mode) Figure 18.18 shows the SCI input/output timing in synchronous mode. SCKr SCKf SCKW...
Page 583: Appendix A Instruction Set
Appendix A Instruction Set Appendix A Instruction Set Instruction List Operand Notation Symbol Description General destination register* General source register* General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) (EAd) Destination operand (EAs)
Page 584 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.3.00 Mar.
Page 585: Data Transfer Instructions
Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z #xx:8 → Rd8 MOV.B #xx:8, Rd — — 0 — Rs8 → Rd8 MOV.B Rs, Rd —...
Page 586 Appendix A Instruction Set No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z W @aa:24 → Rd16 MOV.W @aa:24, Rd — — 0 — W Rs16 → @ERd MOV.W Rs, @ERd — — 0 —...
Page 587 Appendix A Instruction Set No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z W SP–2 → SP PUSH.W Rn 2 — — 0 — Rn16 → @SP SP–4 → SP PUSH.L ERn 4 —...
Page 588 Appendix A Instruction Set 2. Arithmetic instructions No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z Rd8+#xx:8 → Rd8 ADD.B #xx:8, Rd — Rd8+Rs8 → Rd8 ADD.B Rs, Rd — W Rd16+#xx:16 → Rd16 ADD.W #xx:16, Rd —...
Page 589 Appendix A Instruction Set No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z ERd32+1 → ERd32 INC.L #1, ERd — — — ERd32+2 → ERd32 INC.L #2, ERd — — — DAA Rd Rd8 decimal adjust —...
Page 590 Appendix A Instruction Set Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z W ERd32 ÷ Rs16 →ERd32 DIVXU. W Rs, ERd — — (6) (7) — — (Ed: remainder, Rd: quotient) (unsigned division) Rd16 ÷...
Page 591: Logic Instructions
Appendix A Instruction Set 3. Logic instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z Rd8∧#xx:8 → Rd8 AND.B #xx:8, Rd — — 0 — Rd8∧Rs8 → Rd8 AND.B Rs, Rd —...
Page 592: Shift Instructions
Appendix A Instruction Set 4. Shift instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z SHAL.B Rd — — SHAL.W Rd — — SHAL.L ERd — — SHAR.B Rd — — SHAR.W Rd —...
Page 593: Bit Manipulation Instructions
Appendix A Instruction Set 5. Bit manipulation instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z (#xx:3 of Rd8) ← 1 BSET #xx:3, Rd — — — — — — (#xx:3 of @ERd) ← 1 BSET #xx:3, @ERd —...
Page 594 Appendix A Instruction Set No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z (#xx:3 of @ERd) → C BLD #xx:3, @ERd — — — — — (#xx:3 of @aa:8) → C BLD #xx:3, @aa:8 —...
Page 595: Branching Instructions
Appendix A Instruction Set 6. Branching instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z BRA d:8 (BT d:8) — Always — — — — — — If condition is true then BRA d:16 (BT d:16) —...
Page 596 Appendix A Instruction Set Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z Z ∨ (N ⊕ V) BLE d:8 — — — — — — — If condition is true then BLE d:16 —...
Page 597: System Control Instructions
Appendix A Instruction Set 7. System control instructions No. of Addressing Mode and States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z — PC → @–SP TRAPA #x:2 1 — — — — — CCR → @–SP <vector>...
Page 598 Appendix A Instruction Set 8. Block transfer instructions Addressing Mode and No. of States * Instruction Length (bytes) Condition Code Mnemonic Operation H N Z — if R4L ≠ 0 then 8+4n * EEPMOV. B 4 — — — — — — repeat @R5 →...
Page 599: Operation Code Maps
Appendix A Instruction Set Operation Code Maps Table A.2 Operation Code Map (1) Rev.3.00 Mar. 26, 2007 Page 577 of 682 REJ09B0353-0300...
Page 600 Appendix A Instruction Set Table A.2 Operation Code Map (2) Rev.3.00 Mar. 26, 2007 Page 578 of 682 REJ09B0353-0300...
Page 601 Appendix A Instruction Set Table A.2 Operation Code Map (3) Rev.3.00 Mar. 26, 2007 Page 579 of 682 REJ09B0353-0300...
Page 602: Number Of States Required For Execution
Appendix A Instruction Set Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.3 indicates the number of states required per cycle according to the bus size.
Page 603 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions On-Chip External Device Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 2 3 + m Branch address read Stack operation...
Page 604 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS...
Page 605 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16...
Page 606 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8...
Page 607 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd...
Page 608 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR MOV.B #xx:8, Rd...
Page 609 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd...
Page 610 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd...
Page 611 Appendix A Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @–ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB.B Rs, Rd SUB.W #xx:16, Rd...
Page 612: Appendix B Internal I/O Register Field
Appendix B Internal I/O Register Field Appendix B Internal I/O Register Field Addresses Data Bit Names Address Register (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'1C H'1D H'1E H'1F...
Page 613 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'40 FLMCR Flash memory H'41 — — — —...
Page 614 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'60 TSTR — — — STR4 STR3 STR2 STR1 STR0 (all channels)
Page 615 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'82 TCR3 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU channel 3...
Page 616 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'A0 TPMR — — — — G3NOV G2NOV G1NOV G0NOV TPC H'A1 TPCR G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0...
Page 617 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'C0 P1DDR DDR P1 DDR P1 DDR P1 DDR P1 DDR P1 DDR P1...
Page 618 Appendix B Internal I/O Register Field Data Bit Names Address Register Module Name (low) Name Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'E0 ADDRAH H'E1 ADDRAL — — — — —...
Page 619: Function
Appendix B Internal I/O Register Field Function Register Register Address to which Name of on-chip acronym name the register is mapped supporting module TSTR Timer Start Register H'60 ITU (all channels) numbers Initial bit — — — STR4 STR3 STR2 STR1 STR0 values...
Page 620 Appendix B Internal I/O Register Field FLMCR—Flash Memory Control Register H'40 Flash memory Modes Initial value 1 to 4, Read/Write and 6 Modes Initial value 5 and 7 Read/Write Program mode Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase mode...
Page 621 Appendix B Internal I/O Register Field EBR—Erase Block Register H'42 Flash memory Modes Initial value 1 to 4, Read/Write and 6 Modes Initial value 5 to 7 Read/Write Block 7 to 0 Block EB7 to EB0 is not selected (Initial value) Block EB7 to EB0 is selected Note: When not erasing flash memory, EBR should be cleared to H'00.
Page 622 Appendix B Internal I/O Register Field RAMCR—RAM Control Register H'47 Flash Memory — — — — RAMS RAM2 RAM1 — Modes Initial value 1 to 4 Read/Write — — — — — Modes Initial value 5 to 7 R/W * R/W * R/W * Read/Write...
Page 623 Appendix B Internal I/O Register Field FLMSR—Flash Memory Status Register H'4D Flash memory FLER — — — — — — — Initial value Read/Write — — — — — — — Flash memory error Flash memory write/erase protection is disabled (Initial value) An error has occurred during flash memory writing/erasing Flash memory error protection is enabled DIVCR—Division Control Register...
Page 624 Appendix B Internal I/O Register Field MSTCR—Module Standby Control Register H'5E System control PSTOP — MSTOP5 MSTOP4 MSTOP3 — — MSTOP0 Initial value Read/Write — Module standby 0 0 A/D converter operates normally 1 A/D converter is in standby state Module standby 3 0 SCI1 operates normally 1 SCI1 is in standby state...
Page 625 Appendix B Internal I/O Register Field TSTR—Timer Start Register H'60 ITU (all channels) — — — STR4 STR3 STR2 STR1 STR0 Initial value Read/Write — — — Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2...
Page 626 Appendix B Internal I/O Register Field TSNC—Timer Synchro Register H'61 ITU (all channels) — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value Read/Write — — — Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2...
Page 627 Appendix B Internal I/O Register Field TMDR—Timer Mode Register H'62 ITU (all channels) — FDIR PWM4 PWM3 PWM2 PWM1 PWM0 Initial value Read/Write — PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2...
Page 628 Appendix B Internal I/O Register Field TFCR—Timer Function Control Register H'63 ITU (all channels) — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3 Initial value Read/Write — — Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3...
Page 629 Appendix B Internal I/O Register Field TCR0—Timer Control Register 0 H'64 ITU0 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer prescaler 2 to 0 Bit 2 Bit 1 Bit 0 TCNT Clock Source TPSC2 TPSC1 TPSC0 Internal clock: φ...
Page 630 Appendix B Internal I/O Register Field TIOR0—Timer I/O Control Register 0 H'65 ITU0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — I/O control A2 to A0 Bit 2 Bit 1 Bit 0 GRA Function IOA2 IOA1 IOA0 GRA is an output...
Page 631 Appendix B Internal I/O Register Field TIER0—Timer Interrupt Enable Register 0 H'66 ITU0 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled...
Page 632 Appendix B Internal I/O Register Field TSR0—Timer Status Register 0 H'67 ITU0 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] •...
Page 633 Appendix B Internal I/O Register Field TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0 Initial value Read/Write Up-counter GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0 Initial value Read/Write Output compare or input capture register GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 Initial value...
Page 634 Appendix B Internal I/O Register Field TIOR1—Timer I/O Control Register 1 H'6F ITU1 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER1—Timer Interrupt Enable Register 1 H'70 ITU1 —...
Page 635 Appendix B Internal I/O Register Field GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR2—Timer Control Register 2 H'78 ITU2...
Page 636 Appendix B Internal I/O Register Field TIOR2—Timer I/O Control Register 2 H'79 ITU2 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Notes: 1. Bit functions are the same as for ITU0. 2. Channel 2 does not have a compare match toggle output function. If this setting is used, 1 output will be selected automatically.
Page 637 Appendix B Internal I/O Register Field TSR2—Timer Status Register 2 H'7B ITU2 — — — — — IMFB IMFA Initial value Read/Write — — — — — R/(W) R/(W) R/(W) Bit functions are the same as for ITU0 Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition]...
Page 638 Appendix B Internal I/O Register Field GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2 Initial value Read/Write Note: Bit functions are the same as for ITU0. TCR3—Timer Control Register 3 H'82 ITU3...
Page 639 Appendix B Internal I/O Register Field TIER3—Timer Interrupt Enable Register 3 H'84 ITU3 — — — — — OVIE IMIEB IMIEA Initial value Read/Write — — — — — Note: Bit functions are the same as for ITU0. TSR3—Timer Status Register 3 H'85 ITU3 —...
Page 640 Appendix B Internal I/O Register Field GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3 Initial value Read/Write Output compare or input capture register (can be buffered) BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3...
Page 641 Appendix B Internal I/O Register Field TOER—Timer Output Enable Register H'90 ITU (all channels) — — EXB4 EXA4 Initial value Read/Write — — Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA 0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings...
Page 642 Appendix B Internal I/O Register Field TOCR—Timer Output Control Register H'91 ITU (all channels) — — — XTGD — — OLS4 OLS3 Initial value Read/Write — — — — — Output level select 3 0 TIOCB , TOCXA , and TOCXB outputs are inverted 1 TIOCB , TOCXA , and TOCXB outputs are not inverted Output level select 4 0 TIOCA , TIOCA , and TIOCB outputs are inverted...
Page 643 Appendix B Internal I/O Register Field TIOR4—Timer I/O Control Register 4 H'93 ITU4 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 Initial value Read/Write — — Note: Bit functions are the same as for ITU0. TIER4—Timer Interrupt Enable Register 4 H'94 ITU4 —...
Page 644 Appendix B Internal I/O Register Field GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4 Initial value Read/Write Note: Bit functions are the same as for ITU3. BRA4 H/L—Buffer Register A4 H/L H'9C, H'9D ITU4...
Page 645 Appendix B Internal I/O Register Field TPMR—TPC Output Mode Register H'A0 — — — — G3NOV G2NOV G1NOV G0NOV Initial value Read/Write — — — — Group 0 non-overlap 0 Normal TPC output in group 0 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected ITU channel Group 1 non-overlap...
Page 646 Appendix B Internal I/O Register Field TPCR—TPC Output Control Register H'A1 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Group 0 compare match select 1 and 0 Bit 1 Bit 0 ITU Channel Selected as Output Trigger G0CMS1 G0CMS0 TPC output group 0 (TP to TP...
Page 647 Appendix B Internal I/O Register Field NDERB—Next Data Enable Register B H'A2 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 TPC outputs TP to TP * are disabled (NDR15 to NDR8 are not transferred to PB to PB ) TPC outputs TP...
Page 648 Appendix B Internal I/O Register Field NDRB—Next Data Register B H'A4/H'A6 • Same output trigger for TPC output groups 2 and 3 Address H'FFA4 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Next output data for Next output data for TPC output group 3 * TPC output group 2 Address H'FFA6...
Page 649 Appendix B Internal I/O Register Field NDRA—Next Data Register A H'A5/H'A7 • Same output trigger for TPC output groups 0 and 1 Address H'FFA5 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Next output data for Next output data for TPC output group 1 TPC output group 0 Address H'FFA7...
Page 650 Appendix B Internal I/O Register Field TCSR—Timer Control/Status Register H'A8 — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock select 2 to 0 CKS2 CKS1 CKS0 Description φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 Timer enable TCNT is initialized to H'00 and halted TCNT is counting Timer mode select...
Page 651 Appendix B Internal I/O Register Field TCNT—Timer Counter H'A9 (read), H'A8 (write) Initial value Read/Write Count value RSTCSR—Reset Control/Status Register H'AB (read), H'AA (write) WRST RSTOE — — — — — — Initial value Read/Write R/(W) — — — — —...
Page 652 Appendix B Internal I/O Register Field SMR—Serial Mode Register H'B0 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 φ clock φ/4 clock φ/16 clock φ/64 clock Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length...
Page 653 Appendix B Internal I/O Register Field BRR—Bit Rate Register H'B1 SCI0 Initial value Read/Write Serial communication bit rate setting Rev.3.00 Mar. 26, 2007 Page 631 of 682 REJ09B0353-0300...
Page 654 Appendix B Internal I/O Register Field SCR—Serial Control Register H'B2 SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock enable 1 and 0 Bit 1 Bit 2 Clock Selection and Output CKE1 CKE2 Asynchronous mode Internal clock, SCK pin available for generic input/output Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode...
Page 655 Appendix B Internal I/O Register Field TDR—Transmit Data Register H'B3 SCI0 Initial value Read/Write Serial transmit data Rev.3.00 Mar. 26, 2007 Page 633 of 682 REJ09B0353-0300...
Page 656 Appendix B Internal I/O Register Field SSR—Serial Status Register H'B4 SCI0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Multiprocessor bit Multiprocessor bit transfer Multiprocessor bit value in Multiprocessor bit value in receive data is 0 transmit data is 0 Multiprocessor bit value in Multiprocessor bit value in...
Page 657 Appendix B Internal I/O Register Field RDR—Receive Data Register H'B5 SCI0 Initial value Read/Write Serial receive data SCMR—Smart Card Mode Register H'B6 SCI0 — — — — SDIR SINV — SMIF Initial value Read/Write — — — — — Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert...
Page 658 Appendix B Internal I/O Register Field SMR—Serial Mode Register H'B8 SCI1 STOP CKS1 CKS0 Initial value Read/Write Note: Bit functions are the same as for SCI0. BRR—Bit Rate Register H'B9 SCI1 Initial value Read/Write Note: Bit functions are the same as for SCI0. SCR—Serial Control Register H'BA SCI1...
Page 659 Appendix B Internal I/O Register Field SSR—Serial Status Register H'BC SCI1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) Notes: Bit functions are the same as for SCI0. * Only 0 can be written to clear the flag. RDR—Receive Data Register H'BD SCI1...
Page 660 Appendix B Internal I/O Register Field P2DDR—Port 2 Data Direction Register H'C1 Port 2 P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR P2 DDR Initial value Modes 1 and 3 Read/Write — — — —...
Page 661 Appendix B Internal I/O Register Field P3DDR—Port 3 Data Direction Register H'C4 Port 3 P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR P3 DDR Initial value Read/Write Port 3 input/output select 0 Generic input pin 1 Generic output pin P3DR—Port 3 Data Register H'C6...
Page 662 Appendix B Internal I/O Register Field P6DDR—Port 6 Data Direction Register H'C9 Port 6 — — P6 DDR P6 DDR P6 DDR — — P6 DDR Initial value Read/Write — Port 6 input/output select 0 Generic input 1 Generic output P5DR—Port 5 Data Register H'CA Port 5...
Page 663 Appendix B Internal I/O Register Field P8DDR—Port 8 Data Direction Register H'CD Port 8 — — — — — — P8 DDR P8 DDR Initial value Read/Write — — — Port 8 input/output select 0 Generic input 1 Generic output P7DR—Port 7 Data Register H'CE Port 7...
Page 664 Appendix B Internal I/O Register Field P9DDR—Port 9 Data Direction Register H'D0 Port 9 — — P9 DDR P9 DDR P9 DDR Initial value Read/Write — — Port 9 input/output select 0 Generic input 1 Generic output PADDR—Port A Data Direction Register H'D1 Port A PA DDR...
Page 665 Appendix B Internal I/O Register Field PADR—Port A Data Register H'D3 Port A Initial value Read/Write Data for port A pins PBDDR—Port B Data Direction Register H'D4 Port B PB DDR — PB DDR PB DDR PB DDR PB DDR PB DDR PB DDR Initial value...
Page 666 Appendix B Internal I/O Register Field P2PCR—Port 2 Input Pull-Up Control Register H'D8 Port 2 P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR P2 PCR Initial value Read/Write Port 2 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
Page 667 Appendix B Internal I/O Register Field ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 — — — — — — Initial value Read/Write ADDRBH ADDRBL A/D conversion data 10-bit data giving an A/D conversion result ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 —...
Page 668 Appendix B Internal I/O Register Field ADCR—A/D Control Register H'E9 TRGE — — — — — — — Initial value Read/Write — — — — — — — Trigger enable 0 A/D conversion cannot be externally triggered ADTRG 1 A/D conversion starts at the fall of the external trigger signal ( Rev.3.00 Mar.
Page 669 Appendix B Internal I/O Register Field ADCSR—A/D Control/Status Register H'E8 ADIE ADST SCAN Initial value Read/Write R/(W) Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Description Selection Selection...
Page 670 Appendix B Internal I/O Register Field ASTCR—Access State Control Register H'ED Bus controller AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value Read/Write Area 7 to 0 access state control Bits 7 to 0 Number of States in Access Cycle AST7 to AST0 Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas...
Page 671 Appendix B Internal I/O Register Field WCER—Wait Controller Enable Register H'EF Bus controller WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0 Initial value Read/Write Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled MDCR—Mode Control Register H'F1...
Page 672 Appendix B Internal I/O Register Field SYSCR—System Control Register H'F2 System control SSBY STS2 STS1 STS0 NMIEG — RAME Initial value Read/Write — RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit...
Page 673 Appendix B Internal I/O Register Field ADRCR—Address Control Register H'F3 Bus controller — — — — — Modes Initial value 1 and Read/Write — — — — — — — 5 to 7 Initial value Mode 3 Read/Write — — —...
Page 674 Appendix B Internal I/O Register Field ISCR—IRQ Sense Control Register H'F4 Interrupt controller — — IRQ5SC IRQ4SC — — IRQ1SC IRQ0SC Initial value Read/Write , IRQ , IRQ and IRQ sense control 0 Interrupts are requested when IRQ , IRQ , IRQ , and IRQ inputs are low...
Page 675 Appendix B Internal I/O Register Field ISR—IRQ Status Register H'F6 Interrupt controller — — IRQ5F IRQ4F — — IRQ1F IRQ0F Initial value Read/Write — — R/(W)* R/(W) * — — R/(W) * R/(W) * , IRQ , IRQ and IRQ flags Bits 5, 4, 1 and 0 IRQ5F...
Page 676 Appendix B Internal I/O Register Field IPRA—Interrupt Priority Register A H'F8 Interrupt controller IPRA7 IPRA6 — IPRA4 IPRA3 IPRA2 IPRA1 IPRA0 Initial value Read/Write Priority level A7, A6, A4 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) •...
Page 677: Appendix C I/O Block Diagrams
Appendix C I/O Block Diagrams Appendix C I/O Block Diagrams Port 1 Block Diagram Software standby Modes 6 and 7 Hardware standby Modes 1, 3, and 5 Reset WP1D Modes 6 and 7 Reset Modes 1, 3, and 5 Legend: WP1D: Write to P1DDR WP1:...
Page 678: Port 2 Block Diagram
Appendix C I/O Block Diagrams Port 2 Block Diagram Reset Modes Software standby RP2P 6 and 7 WP2P Hardware standby Modes 1, 3, and 5 Reset WP2D Modes 6 and 7 Reset Modes 1, 3, and 5 Legend: WP2P: Write to P2PCR RP2P: Read P2PCR WP2D:...
Page 679: Port 3 Block Diagram
Appendix C I/O Block Diagrams Port 3 Block Diagram Reset Hardware Modes 6 and 7 standby Write to external address WP3D Reset Modes 6 and 7 Modes 1, 3, and 5 Read external address Legend: WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3...
Page 680: Port 5 Block Diagram
Appendix C I/O Block Diagrams Port 5 Block Diagram Reset Software standby Modes RP5P 6 and 7 Hardware standby WP5P Modes 1, 3 Reset WP5D Modes 6 and 7 Reset Modes 1, 3, and 5 Legend: WP5P: Write to P5PCR RP5P: Read P5PCR WP5D:...
Page 681: Port 6 Block Diagram
Appendix C I/O Block Diagrams Port 6 Block Diagram Reset Bus controller Modes 6 and 7 WP6D WAIT Reset input enable Bus controller WAIT output Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.5 (a) Port 6 Block Diagram (Pin P6 Rev.3.00 Mar.
Page 682 Appendix C I/O Block Diagrams Software standby Modes 6 and 7 Hardware standby Reset WP6D Reset Modes 6 and 7 Modes 1, 3, and 5 AS output RD output WR output Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Note: n = 3 to 5...
Page 683: Port 7 Block Diagram
Appendix C I/O Block Diagrams Port 7 Block Diagram A/D converter Input enable Analog input Legend: RP7: Read port 7 Note: n = 0 to 7 Figure C.6 Port 7 Block Diagram Rev.3.00 Mar. 26, 2007 Page 661 of 682 REJ09B0353-0300...
Page 684: Port 8 Block Diagram
Appendix C I/O Block Diagrams Port 8 Block Diagram Reset WP8D Reset Interrupt controller input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.7(a) Port 8 Block Diagram (Pin P8 Rev.3.00 Mar. 26, 2007 Page 662 of 682 REJ09B0353-0300...
Page 685 Appendix C I/O Block Diagrams Reset WP8D Reset Modes 6 and 7 Modes 1, 3, and 5 Interrupt controller input Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.7 (b) Port 8 Block Diagram (Pin P8 Rev.3.00 Mar.
Page 686: Port 9 Block Diagram
Appendix C I/O Block Diagrams Port 9 Block Diagram Reset WP9D Reset SCI0 Output enable Serial transmit data Guard time Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.8 (a) Port 9 Block Diagram (Pin P9 Rev.3.00 Mar.
Page 687 Appendix C I/O Block Diagrams Reset WP9D Reset SCI1 Output enable Serial transmit data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.8 (b) Port 9 Block Diagram (Pin P9 Rev.3.00 Mar. 26, 2007 Page 665 of 682 REJ09B0353-0300...
Page 688 Appendix C I/O Block Diagrams Reset WP9D Input enable Reset Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 2, 3 Figure C.8 (c) Port 9 Block Diagram (Pin P9 , P9 Rev.3.00 Mar.
Page 689 Appendix C I/O Block Diagrams Reset WP9D Clock input enable Reset Clock output enable Clock output Clock input Interrupt controller input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 4 and 5 Figure C.8 (d) Port 9 Block Diagram (Pin P9 , P9 Rev.3.00 Mar.
Page 690: Port A Block Diagram
Appendix C I/O Block Diagrams Port A Block Diagram Reset WPAD Reset TPC output enable Next data Output trigger Counter input clock Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 0 or 1 Figure C.9 (a) Port A Block Diagram (Pins PA , PA Rev.3.00 Mar.
Page 691 Appendix C I/O Block Diagrams Reset WPAD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input Counter input clock Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 2 or 3 Figure C.9 (b) Port A Block Diagram (Pins PA , PA...
Page 692 Appendix C I/O Block Diagrams Software standby Address output enable Mode 3 Reset WPAD TPC output Reset enable Next data Output trigger Output enable Compare match output Input capture input Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Notes: n = 4 to 7...
Page 693: Port B Block Diagram
Appendix C I/O Block Diagrams C.10 Port B Block Diagram Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output Input capture input Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 0 to 3 Figure C.10 (a) Port B Block Diagram (Pins PB to PB...
Page 694 Appendix C I/O Block Diagrams Reset WPBD Reset TPC output enable Next data Output trigger Output enable Compare match output Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 4 or 5 Figure C.10 (b) Port B Block Diagram (Pins PB , PB Rev.3.00 Mar.
Page 695 Appendix C I/O Block Diagrams Reset WPBD Reset TPC output enable Next data Output trigger A/D converter ADTRG input Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.10 (c) Port B Block Diagram (Pin PB Rev.3.00 Mar.
Page 696: Appendix D Pin States
Appendix D Pin States Appendix D Pin States Port States in Each Mode Table D.1 Port States Reset Hardware Software Program Execution Pin Name Mode State Standby Mode Standby Mode State Sleep Mode φ — Clock Clock output output RESO* RESO —...
Page 697 Appendix D Pin States Reset Hardware Software Program Execution Pin Name Mode State Standby Mode Standby Mode State Sleep Mode 1, 3, 5 T [DDR = 0] Input port [DDR = 0] H [DDR = 1] H [DDR = 1] 6, 7 keep I/O port...
Page 698: Pin States At Reset
Appendix D Pin States Pin States at Reset Reset in T1 State Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state.
Page 699 Appendix D Pin States Reset in T2 State Figure D.2 is a timing diagram for the case in which RES goes low during the T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state.
Page 700 Appendix D Pin States Reset in T3 State Figure D.3 is a timing diagram for the case in which RES goes low during the T state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state.
Page 701: Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below.
Page 702: Appendix F Product Lineup
Appendix F Product Lineup Appendix F Product Lineup Table F.1 H8/3039 Group Product Lineup Package Product Type Part Number Mark Code (Package Code) H8/3039 Flash memory HD64F3039F HD64F3039F 80-pin QFP (FP-80A) version version HD64F3039TE HD64F3039TE 80-pin TQFP (TFP-80C) HD64F3039VF HD64F3039VF 80-pin QFP (FP-80A) version HD64F3039VTE...
Page 703: Appendix G Package Dimensions
Appendix G Package Dimensions Appendix G Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP80-14x14-0.65 PRQP0080JB-A FP-80A/FP-80AV 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Page 704 Appendix G Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TQFP80-12x12-0.50 PTQP0080KC-A TFP-80C/TFP-80CV 0.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Reference Terminal cross section Symbol 1.00 13.8 14.0...
Page 705 Publication Date: 1st Edition, December 1997 Rev.3.00, March 26, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 706 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 708 H8/3039 Group, H8/3039F-ZTAT™ Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...