Master Transmit Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.5.3

Master Transmit Operation

In master transmit operation, the RIIC outputs the SCL (clock) and transmitted data signals as the
master device, and the slave device returns acknowledgements. Figure 18.6 shows an example of
usage of master transmission and Figure 18.7 to Figure 18.9 show the timing of operations in master
transmission.
The following describes the procedure and operations for master transmission.
(1) Set the RIICnCR1.IICRST bit 1 to 1 (RIIC reset) and then set the RIICnCR1.ICE bit to 1
(internal reset) with the RIICnCR1.ICE bit cleared to 0 (RIICnSCL and RIICnSDA pins not
driven). This initializes the internal state and the various flags of RIICnSR1. After that, set
registers RIICnSARy, RIICnSER, RIICnMR1, RIICnBRH, and RIICnBRL (y = 0 to 2), and set
the other registers as necessary (for initial settings of the RIIC, see Figure 18.5). When the
necessary register settings have been completed, set the RIICnCR1.IICRST bit to 0 (for release
from the reset state). This step is not necessary if initialization of the RIIC has already been
completed.
(2) Read the RIICnCR2.BBSY flag to check that the bus is open, and then set the RIICnCR2.ST bit
to 1 (start condition issuance request). Upon receiving the request, the RIIC issues a start
condition. At the same time, the BBSY flag and the RIICnSR2.START flag are automatically set
to 1 and the ST bit is automatically cleared to 0. At this time, if the start condition is detected and
the internal levels for the SDA output state and the levels on the SDA line have matched while
the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested by the ST bit
has been successfully completed, and the RIICnCR2.MST and TRS bits are automatically set to
1, placing the RIIC in master transmit mode. The RIICnSR2.TDRE flag is also automatically set
to 1 in response to setting of the TRS bit to 1.
(3) Check that the RIICnSR2.TDRE flag is 1, and then write the value for transmission (the slave
address and the R/W# bit) to RIICnDRT. Once the data for transmission are written to
RIICnDRT, the TDRE flag is automatically cleared to 0, the data are transferred from RIICnDRT
to RIICnDRS, and the TDRE flag is again set to 1. After the byte containing the slave address and
R/W# bit has been transmitted, the value of the TRS bit is automatically updated to select master
transmit or master receive mode in accord with the value of the transmitted R/W# bit. If the value
of the R/W# bit was 0, the RIIC continues in master transmit mode.
Since the RIICnSR2.NACKF flag being 1 at this time indicates that no slave device recognized
the address or there was an error in communications, write 1 to the RIICnCR2.SP bit to issue a
stop condition.
For data transmission with an address in the 10-bit format, start by writing 1111 0
higher-order bits of the slave address, and W# to RIICnDRT as the first address transmission.
Then, as the second address transmission, write the eight lower-order bits of the slave address to
RIICnDRT.
(4) After confirming that the RIICnSR2.TDRE flag is 1, write the data for transmission to the
RIICnDRT register. The RIIC automatically holds the SCL line low until the data for
transmission are ready or a stop condition is issued.
(5) After the last byte of the data to be transmitted is written to RIICnDRT register, wait until the
value of the RIICnSR2.TEND flag returns to 1, and then set the RIICnCR2.SP bit to 1 (stop
condition issuance request). Upon receiving a stop condition issuance request, the RIIC issues the
stop condition.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
18. I²C Bus Interface
, the two
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