Flash Control Register (Flash_Cr) - STMicroelectronics STM32WLEx Reference Manual

RM0461
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Bit 0 EOP: End of operation
3.8.5

FLASH control register (FLASH_CR)

Address offset: 0x014
Reset value: 0xC000 0000
Access: no wait state when no flash memory operation is ongoing. Word, half-word and byte
access.
This register cannot be modified when CFGBSY is set in FLASH_SR.
When PESD is cleared in FLASH_SR, the register write access is stalled until the CFGBSY
bit is cleared.
When PESD is set in FLASH_SR and a program or an erase operation is ongoing, the
register write access causes a bus error.
When PESD is set in FLASH_SR but there is no ongoing programming or erase operation,
the register write access is completed, but the requested operation is suspended.
BSY/CFGBSY is set and remains 1 until suspend is deactivated by clearing the PES bits in
FALSH_ACR. Consequently PESD goes back to 0 and the suspended operation completes.
31 30 29 28
LOCK Res. Res.
rs rs
15 14 13 12
Res. Res. Res. Res.
This bit is set by hardware when a flash memory operation (program/erase) completes
unsuccessfully. This bit is set only if error interrupts are enabled (ERRIE = 1).
This bit is cleared by writing 1.
This bit is set by hardware when one or more flash memory operation (program/erase)
completes successfully. This bit is set only if the end of operation interrupts are enabled
(EOPIE = 1).
This bit is cleared by writing 1.
27 26 25
ERRIE
rc_w1 rw rw
11 10
Res. Res.
rw
24 23 22
EOPIE Res. Res.
rw
9 8 7 6
PNB[6:0]
rw rw rw
RM0461 Rev 5
Embedded flash memory (FLASH)
21 20 19 18
Res. Res. Res. FSTPG
rw
5 4 3 2
MER
rw rw rw rw
17 16
STRT
rs rs
1 0
PER PG
rw rw
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