Table 109. Adc Interrupts; Figure 85. Vbat Channel Block Diagram - STMicroelectronics STM32WL5 Series Reference Manual

Analog-to-digital converter (ADC)
the correct operation of the ADC, the VBAT pin is internally connected to a bridge divider.
This bridge is automatically enabled when VBATEN is set, to connect V
V [14] input channel. As a consequence, the converted digital value is V
IN
any unwanted consumption on the battery, it is recommended to enable the bridge divider
only when needed for ADC conversion.
18.11 ADC interrupts
An interrupt can be generated by any of the following events:
•
End Of Calibration (EOCAL flag)
•
ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
•
End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD1, AWD2, AWD3 flags)
•
When the Channel configuration is ready (CCRDY flag)
• When the end of sampling phase occurs (EOSMP flag)
•
when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.
End Of Calibration
ADC ready
End of conversion
End of sequence of conversions
Analog watchdog 1 status bit is set
568/1450
Figure 85. V
VBATEN control bit
V
BAT
V /3
BAT
+
-

Table 109. ADC interrupts

Interrupt event
RM0453 Rev 5
channel block diagram
BAT
ADC
ADC V
IN
Event flag
to the ADC
BAT
/3. To prevent
BAT
[14]
Enable control bit
EOCAL EOCALIE
ADRDY ADRDYIE
EOC EOCIE
EOS EOSIE
AWD1 AWD1IE
RM0453
MSv69533V1