ST STM32L4+ Series Reference Manual page 1299

RM0432
Table 277. TIM1 register map and reset values (continued)
Register
Offset
name
TIM1_CNT
0x24
Reset value
0
TIM1_PSC
0x28
Reset value
TIM1_ARR
0x2C
Reset value
TIM1_RCR
0x30
Reset value
TIM1_CCR1
0x34
Reset value
TIM1_CCR2
0x38
Reset value
TIM1_CCR3
0x3C
Reset value
TIM1_CCR4
0x40
Reset value
TIM1_BDTR
0x44
Reset value
TIM1_DCR
0x48
Reset value
TIM1_DMAR
0x4C
Reset value
TIM1_OR1
0x50
Reset value
TIM1_CCMR3
Output
0x54
Compare mode
Reset value
BK2F[3:0]
0 0 0 0 0 0 0 0 0
0
RM0432 Rev 6
Advanced-control timers (TIM1/TIM8)
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
BKF[3:0]
0 0 0 0 0 0 0 0 0
0
DMAB[31:0]
0 0 0 0
OC6M
[2:0]
0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1 1
REP[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
LOC
K DT[7:0]
[1:0]
0 0 0 0 0 0 0 0 0
DBL[4:0] DBA[4:0]
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
OC5M
[2:0]
0 0 0 0 0 0 0
1299/2301
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0
0
1302