Clock Pulse Generator; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.

Clock Pulse Generator

This LSI has a clock pulse generator that generates a CPU clock (Iφ), internal bus clock (Bφ), peripheral clock 1 (P1φ),
and peripheral clock 0 (P0φ). The clock pulse generator consists of a crystal oscillator, PLL circuits, and divider circuits.
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Features

• Clock types
A CPU clock (Iφ); an internal bus clock (Bφ); peripheral clock 1 (P1φ = CKIO) for the external bus interface;
peripheral clock 0 (P0φ) for the on-chip peripheral modules
• Frequency change function
The CPU clock frequency can be changed using the PLL (phase locked loop) circuits and divider circuits within this
module. The frequency is changed by software using frequency control register (FRQCR) setting.
• Power-down mode control
The clock can be stopped in sleep mode, software standby mode, and deep standby mode, and specific modules can
be stopped using the module standby function. For details on clock control in the power-down modes, see section
42, Power-Down Modes.
• SSCG function
The CPU's internal PLL (phase locked loop) circuit includes an SSCG (spread spectrum clock generator).
The SSCG can be used to decrease the peak value of EMI (electromagnetic interference) noise by frequency
modulation, that is, by slightly modulating the output frequency.
The specification of the SSCG for this LSI is as follows.
—Specification of SSCG
(1) Modulation waveform (modulation profile): Triangle wave
(2) Type of spreading: Down-spreading
(3) Modulation rate: -3.3% (clock mode 0), -3.1% (clock mode 1)
(4) Modulation frequency: 20.00 to 26.67 kHz (frequency on the EXTAL pin ÷ 500)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
24.00 kHz (frequency on the USB_X1 pin x (1/4) ÷ 500)
6. Clock Pulse Generator
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