Table of Contents
Advertisement
This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock,
bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, duty
correction circuit, system clock select circuit, subclock input circuit, and subclock waveform
forming circuit. Figure 25.1 shows a block diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
Subclock
EXCL
input circuit
(ExEXCL)
Figure 25.1 Block Diagram of Clock Pulse Generator
The subclock input is controlled by software according to the EXCLE bit and the EXCLS bit in
the port control register (PTCNT0) settings in the low power control register (LPWRCR). For
details on LPWRCR, see section 26.1.2, Low-Power Control Register (LPWRCR). For details on
PTCNT0, see section 8.3.1, Port Control Register 0 (PTCNT0).
Section 25 Clock Pulse Generator
Duty
correction
circuit
Subclock
waveform
forming circuit
φ
System
clock
select
φ
circuit
φSUB
System clock
to φ pin
WDT_1
count clock,
CIR
sampling clock
Rev. 1.00 May 09, 2008 Page 801 of 954
Section 25 Clock Pulse Generator
Bus master
clock to CPU
Internal clock
to on-chip
peripheral modules
REJ09B0462-0100
Advertisement
Table of Contents
