Section 19 Clock Pulse Generator; Figure 19.1 Block Diagram Of Clock Pulse Generator - Renesas H8S Series Hardware Manual

Section 19 Clock Pulse Generator

This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock
selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block
diagram of the clock pulse generator is shown in figure 19.1.
EXTAL
Clock
oscillator
XTAL
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register

Figure 19.1 Block Diagram of Clock Pulse Generator

The frequency can be changed by means of the PLL circuit. Frequency changes are performed by
software by settings in the low-power control register (LPWRCR) and system clock control
register (SCKCR).
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
Clock
selection
circuit
Section 19 Clock Pulse Generator
Medium-
speed
φ/2 to
clock divider
System clock Internal clock to
to φ pin
supporting modules
Rev. 6.00 Mar 15, 2006 page 481 of 570
SCKCR
SCK2 to SCK0
Bus
φ/32
master
clock
selection
circuit
φ
Bus master clock
to CPU and DTC
REJ09B0211-0600