Section 20 Clock Pulse Generator; Overview; Block Diagram; Register Configuration - Renesas H8S Series Hardware Manual

20.1

Overview

The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock,
and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a
bus master clock selection circuit.
20.1.1

Block Diagram

Figure 20-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
20.1.2

Register Configuration

The clock pulse generator is controlled by SCKCR. Table 20-1 shows the register configuration.
Table 20-1 Clock Pulse Generator Register
Name
System clock control register
Note:* Lower 16 bits of the address.

Section 20 Clock Pulse Generator

Duty
Oscillator
adjustment
circuit
System clock to ø pin
Figure 20-1 Block Diagram of Clock Pulse Generator
Abbreviation
SCKCR
SCKCR
Medium-
speed
Bus master
divider ø/2 to ø/32
selection
circuit
Internal clock
to supporting
modules
R/W Initial Value
R/W H'00
Rev.6.00 Oct.28.2004 page 661 of 1016
SCK2 to SCK0
clock
Bus master clock
to CPU, DTC,
and DMAC
Address*
H'FF3A
REJ09B0138-0600H