Section 18 Clock Pulse Generator; Figure 18.1 Block Diagram Of Clock Pulse Generator - Renesas H8SX/1520 Series Hardware Manual

This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (Iφ),
peripheral module clock (Pφ), and external clock (Bφ).
The clock pulse generator consists of an oscillator, PLL (Phase Locked Loop) circuit, and divider.
Figure 18.1 shows a block diagram of the clock pulse generator.
Clock frequencies can be changed by the PLL circuit and divider in the CPG. Changing the
system clock control register (SCKCR) setting by software can change the clock frequencies.
This LSI supports three types of clocks: a system clock provided to the CPU and bus masters, a
peripheral module clock provided to the peripheral modules, and an external clock provided to the
external bus. These clocks can be specified independently. Note, however, that the frequencies of
the peripheral clock and external clock are lower than that of the system clock.
EXTAL
Oscillator
XTAL
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Section 18 Clock Pulse Generator

EXTAL × 8
PLL
circuit

Figure 18.1 Block Diagram of Clock Pulse Generator

SCKCR
1/1
1/2
Selector
1/4
1/8
SCKCR
Divider
1/1
(1/1,
1/2
Selector
1/2,
1/4
1/4,
1/8
and 1/8)
SCKCR
1/1
1/2
Selector
1/4
1/8
Rev. 3.00 Mar. 14, 2006 Page 661 of 804
Section 18 Clock Pulse Generator
ICK2 to ICK0
System clock (Iφ)
(to the CPU and
bus masters)
PCK2 to PCK0
Peripheral module
clock (Pφ)
(to peripheral modules)
BCK2 to BCK0
External bus clock (Bφ)
(to the Bφ pin)
REJ09B0104-0300