Section 23A Clock Pulse Generator; (H8S/2633, H8S/2632, H8S/2631, H8S/2633F); Overview; 1.1 Block Diagram - Renesas H8S/2633 Series Hardware Manual

Section 23A Clock Pulse Generator

(H8S/2633, H8S/2632, H8S/2631, H8S/2633F)

23A.1 Overview
The H8S/2633 Series has a built-in clock pulse generator (CPG) that generates the system clock
(ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
23A.1.1 Block Diagram
Figure 23A-1 shows a block diagram of the clock pulse generator.
EXTAL
System
clock
oscillator
XTAL
OSC1
Subclock
oscillator
OSC2
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
Figure 23A-1 Block Diagram of Clock Pulse Generator
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
Clock
selection
circuit
ø SUB
Waveform
shaping
circuit
WDT1 count clock
Medium-
speed
clock divider
System clock Internal clock to
to ø pin supporting modules
SCKCR
SCK2 to SCK0
ø/2 to
Bus
ø/32
master
clock
selection
circuit
ø
Bus master clock
to CPU, DMAC
and DTC
959