Flash Memory Control Register 2 (Flmcr2) - Renesas F-ZTAT H8 Series Hardware Manual

Section 18 ROM
18.5.2

Flash Memory Control Register 2 (FLMCR2)

FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'40000 to H'7FFFF is entered by setting SWE2 to 1 when
FWE (FLMCR1) = 1, then setting the EV2 or PV2 bit. Program mode for addresses H'40000 to
H'7FFFF is entered by setting SWE2 to 1 when FWE (FLMCR1) = 1, then setting the PSU2 bit,
and finally setting the P2 bit. Erase mode for addresses H'40000 to H'7FFFF is entered by setting
SWE2 to 1 when FWE (FLMCR1) = 1, then setting the ESU2 bit, and finally setting the E2 bit.
FLMCR2 is initialized to H'00 by a power-on reset, in hardware standby mode and software
standby mode, when a low level is input to the FWE pin, and when a high level is input to the
FWE pin and the SWE2 bit in FLMCR2 is not set (the exception is the FLER bit, which is
initialized only by a power-on reset and in hardware standby mode). When on-chip flash memory
is disabled, a read will return H'00, and writes are invalid.
Writes are enabled only in the following cases: Writes to bit SWE2 of FLMCR2 enabled when
FWE (FLMCR1) = 1, to bits ESU2, PSU2, EV2, and PV2 when FEW (FLMCR1) = 1 and SWE2
= 1, to bit E2 when FWE (FLMCR1) = 1, SWE2 = 1, and ESU2 = 1, to bit P2 when FWE
(FLMCR1) = 1, SWE2 = 1, and PSU2 = 1.
Bit 7
FLER
Initial value 0
Read/Write R
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7: FLER Description
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Power-on reset or hardware standby mode
An error has occurred during flash memory programming/erasing
1
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See 18.8.3 Error Protection
Rev. 3.00 Mar 21, 2006 page 568 of 814
REJ09B0302-0300
6 5
SWE2 ESU2
0 0
R/W R/W
4 3
PSU2 EV2
0 0
R/W R/W
2 1
PV2 E2
0 0
R/W R/W R/W
(Initial value)
0
P2
0