Flash Memory Control Register 2 (Flmcr2) - Renesas F-ZTAT H8 Series Hardware Manual

6.3.2

Flash Memory Control Register 2 (FLMCR2)

Bit
FLER
Initial value
Read/Write
FLMCR2 is an 8-bit register used for monitoring of flash memory program/erase protection (error
protection) and for flash memory program/erase mode setup. FLMCR2 is initialized to H'00 by a
reset. The ESU and PSU bits are cleared to 0 in standby mode, hardware protect mode, and
software protect mode.
Bit 7—Flash Memory Error (FLER): Bit 7 indicates that an error has occurred during an
operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes
to the error-protection state.
Bit 7: FLER Description
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset
1 An error occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 6.6.3, Error Protection
Bits 6 to 2—Reserved Bits: Bits 6 to 2 are reserved; they are always read as 0 and cannot be
modified.
Bit 1—Erase Setup (ESU)*: Bit 1 prepares for a transition to erase mode. Set this bit to 1 before
setting the E bit in FLMCR1. (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.)
Bit 1: ESU Description
0 Erase setup cleared
1 Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
7 6 5
⎯ ⎯
0 0 0
⎯ ⎯
R
4 3 2
⎯ ⎯ ⎯
0 0 0
⎯ ⎯ ⎯
Rev.3.00 Jul. 19, 2007 page 129 of 532
6. ROM
1 0
ESU PSU
0 0
R/W R/W
(initial value)
(initial value)
REJ09B0397-0300