Flash Memory Power Control Register (Flpwcr); Table 6.7 Division Of Blocks To Be Erased - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Division of Blocks to Be Erased

Flash Memory Power Control Register (FLPWCR)

Initial value

FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI

switches to subactive mode. The power supply circuit can be read in the subactive mode, although

it is partly halted in the power-down mode.

Bit 7—Power-down Disable (PDWND)

This bit selects the power-down mode of the flash memory when a transition to the subactive

mode is made.

When this bit is 0 and a transition is made to the subactive mode, the flash memory

enters the power-down mode.

When this bit is 1, the flash memory remains in the normal mode even after a

transition is made to the subactive mode.

Bits 6 to 0—Reserved

These bits are always read as 0 and cannot be modified.

Block (Size)

EB0 (1 Kbyte)

EB1 (1 Kbyte)

EB2 (1 Kbyte)

EB3 (1 Kbyte)

EB4 (28 Kbytes)

EB5 (16 Kbyte)

EB6 (8 Kbyte)

EB7 (4 Kbytes)

H'0000 to H'03FF

H'0400 to H'07FF

H'0800 to H'0BFF

H'0C00 to H'0FFF

H'1000 to H'7FFF

H'8000 to H'BFFF

H'C000 to H'DFFF

H'E000 to H'EFFF

Rev. 6.00 Aug 04, 2006 page 175 of 680

Section 6 ROM

(initial value)

REJ09B0145-0600