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Section 27 Power-Down Modes
Table 27.1 Operating Frequency and Wait Time
STS2
STS1
STS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Recommended specification
Note:
* This setting cannot be made in the flash-memory version of this LSI.
27.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit
Bit Name Initial Value R/W
7
DTON
0
Rev. 3.00 Jan 25, 2006 page 774 of 872
REJ09B0286-0300
Wait Time
24M Hz 20 MHz 10 MHz 8 MHz
8192 states
0.3
16384 states
0.7
32768 states
1.3
65536 states
2.7
131072 states
5.5
262144 states
10.9
Reserved
16 states *
0.7
Description
R/W
Direct Transfer On Flag
Specifies the operating mode to be entered after executing
the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or watch
mode
1: Shifts directly to subactive mode, or shifts to sleep mode
or software standby mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode or watch mode
1: Shifts directly to high-speed mode, or shifts to subsleep
mode
0.4
0.8
1.0
0.8
1.6
2.0
2.0
3.3
4.1
4.1
6.6
8.2
8.2
13.1
16.4
16.4
26.2
32.8
0.8
1.6
2.0
6 MHz
Unit
1.3
ms
2.7
5.5
10.9
21.8
43.6
µs
2.7
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