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26.1.2
Low-Power Control Register (LPWRCR)
LPWRCR controls power-down modes.
Bit
Bit Name
7
DTON
6
LSON
5
NESEL
4
EXCLE
3 to 0
Initial
Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
All 0
R/W
Description
Direct Transfer On Flag
The initial value should not be changed.
Low-Speed On Flag
The initial value should not be changed.
Noise Elimination Sampling Frequency Select
Selects the frequency by which the subclock (φSUB)
input from the EXCL or ExEXCL pin is sampled using
the clock (φ) generated by the system clock pulse
generator. The initial value should not be changed.
0: Sampling using φ/32 clock
1: Sampling using φ/4 clock (setting prohibited)
Subclock Input Enable
Enables or disables subclock input from the EXCL or
ExEXCL pin.
0: Disables subclock input from the EXCL or ExEXCL
pin
1: Enables subclock input from the EXCL or ExEXCL
pin
Reserved
The initial value should not be changed.
Rev. 1.00 May 09, 2008 Page 813 of 954
Section 26 Power-Down Modes
REJ09B0462-0100
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