Control Registers; Power Save Control Register (Psc); Power Save Control Register (Psc) - Renesas NU85E Preliminary User's Manual

6.2 Control Registers

6.2.1 Power save control register (PSC)

The PSC is an 8-bit register that controls the power save function.
If interrupts are enabled according to the NMI2M to NMI0M and INTM bit settings, software STOP mode can be
canceled by an interrupt request (except when interrupt servicing is disabled by the interrupt mask register (IMR0 to
IMR3)).
Software STOP mode is specified by setting the STP bit.
This register can only be written by using a specific procedure so that its settings are not mistakenly overwritten
due to erroneous program execution.
This register can be read or written in 8-bit or 1-bit units.
Caution Do not set the PSC register by transferring data using the DMAC. To set this register, always use
a store instruction (ST or SST) or a bit manipulation instruction (SET1, CLR1, or NOT1
instruction).
7 6
PSC NMI2M NMI1M
Bit position Bit name
7 NMI2M
6 NMI1M
5 NMI0M
4 INTM
1 STP
Note The setting is valid in software STOP mode only.
Cautions 1. If the NMI2M to NMI0M and INTM bits are set (1) at the same time as the STP bit, the settings
of the NMI2M to NMI0M and INTM bits are invalid. Therefore, if there are unmasked interrupt
requests pending when software STOP mode is entered, be sure to set (1) those interrupt
request bits (NMI2M to NMI0M and INTM) before setting (1) the STP bit.
2. Because an interrupt request that occurs while the NMI2M to NMI0M and INTM bits are set (1)
is invalid (it is not held pending), software STOP mode cannot be canceled.
CHAPTER 6 STBC
Figure 6-2. Power Save Control Register (PSC)
5 4
NMI0M INTM
Masks non-maskable interrupt requests (NMI2) from the DCNMI2 pin.
0: Enables NMI2 requests
1: Disables NMI2 requests
Masks non-maskable interrupt requests (NMI1) from the DCNMI1 pin.
0: Enables NMI1 requests
1: Disables NMI1 requests
Masks non-maskable interrupt requests (NMI0) from the DCNMI0 pin.
0: Enables NMI0 requests
1: Disables NMI0 requests
Masks maskable interrupt requests (INT63 to INT0) from the INT63 to INT0 pins.
0: Enables INT63 to INT0 requests
1: Disables INT63 to INT0 requests
Specifies software STOP mode.
When this bit is set (1), software STOP mode is set. When software STOP mode is canceled,
this bit is automatically cleared (0).
Preliminary User's Manual A14874EJ3V0UM
3 2 1
0 0 STP
Function
0
Address After reset
0
FFFFF1FEH 00H
Note
Note
Note
Note
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