Low-Power Control Register (Lpwrcr) - Renesas H8S Series Hardware Manual

Bit Bit Name
3 STCS
2 SCK2
1 SCK1
0 SCK0
Legend:
X: Don't care
19.1.2

Low-Power Control Register (LPWRCR)

Bit Bit Name
7 to —
4
3, 2 —
1 STC1
0 STC0
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
All 0 —
All 0 R/W
0 R/W
0 R/W
Section 19 Clock Pulse Generator
Description
Frequency Multiplication Factor Switching Mode
Select
Selects the operation when the PLL circuit
frequency multiplication factor is changed.
0: Specified multiplication factor is valid after
transition to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 bit and STC0 bit are rewritten
System Clock Select 0 to 2
These bits select the bus master clock.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11X: Setting prohibited
Description
Reserved
Only 0 should be written to these bits.
These bits can be read and write, but should not be
set to 1.
Frequency Multiplication Factor
The STC bits specify the frequency multiplication
factor of the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
Rev. 6.00 Mar 15, 2006 page 483 of 570
REJ09B0211-0600