Low-Power Control Register (Lpwrcr); Table 20.1 Operating Frequency And Wait Time - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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Table 20.1 Operating Frequency and Wait Time

STS2 STS1 STS0 Wait Time
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Shaded cells indicate the recommended specification.
20.1.2

Low-Power Control Register (LPWRCR)

LPWRCR controls power-down modes.
Bit
Bit Name
7
DTON
8192 states
16384 states
32768 states
65536 states
131072 states
262144 states
Reserved
Reserved
Initial
Value
R/W
0
R/W
10 MHz
8 MHz
0.8
1.0
1.6
2.0
3.3
4.1
6.6
8.2
13.1
16.4
26.2
32.8
Description
Direct Transfer On Flag
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-speed
mode or medium-speed mode:
0: Shifts to sleep mode, software standby mode, or
watch mode
1: Shifts directly to subactive mode, or shifts to sleep
mode or software standby mode
When the SLEEP instruction is executed in subactive
mode:
0: Shifts to subsleep mode or watch mode
1: Shifts directly to high-speed mode, or shifts to
subsleep mode
6 MHz
4 MHz
1.3
20.
2.7
4.1
5.5
8.2
10.9
16.4
21.8
32.8
43.6
65.6
Rev. 1.00, 05/04, page 465 of 544
Unit
ms

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