Renesas RZ/A1LU Manuals

Manuals and User Guides for Renesas RZ/A1LU. We have 2 Renesas RZ/A1LU manuals available for free PDF download: User Manual, Manuallines

Renesas RZ/A1LU User Manual

Renesas RZ/A1LU User Manual (2866 pages)

Brand: Renesas | Category: Computer Hardware | Size: 41 MB

Table of Contents

Table of Contents
4
Overview
52
Features of this LSI
52
Product Lineup
60
Block Diagram
60
Pin Assignment
61
Pin Functions
65
List of Pins
71
Cpu
79
Features
79
Configuration Signals
80
Boot Mode
81
Features
81
Boot Mode and Pin Function Setting
81
Hardware Used in each Boot Mode
82
Exception Vector Address at a Reset in each Boot Mode
83
Boot Mode 0
83
Boot Mode 1
84
Boot Mode 2
85
Boot Mode 3
87
Notes
89
Boot Related Pins
89
Operation When an Exception Occurs with the Exception Vector Set to the High Vector Address
89
Notes on Serial Flash Booting (Boot Mode 1) after this LSI Is Reset
89
Secondary Cache
90
Features
90
Configuration Signals
90
LSI Internal Bus
91
Configuration
91
Operation
91
North Main Bus
92
Configuration
92
Features
92
Peripheral Buses
93
South Main Bus
95
Configuration
95
Features
95
Connected Buses
96
Address Map
97
Address Remapping
100
Overview
100
Operation
100
AXI Interconnect
101
Configuration
101
Operation
101
Bus Bridges
101
AXI Protocol Control Signals
102
Bus Masters Other than Cortex-A9, Coresight, and the Direct Memory Access Controller
102
Cortex-A9
102
Coresight
102
Direct Memory Access Controller
103
Slave Area
103
Write Buffers
103
Register Descriptions
104
Remap Register (RMPR)
105
AXI Bus Control Register 0 (AXIBUSCTL0)
106
AXI Bus Control Register 2 (AXIBUSCTL2)
107
AXI Bus Control Register 5 (AXIBUSCTL5)
107
AXI Bus Control Register 6 (AXIBUSCTL6)
108
AXI Bus Control Register 7 (AXIBUSCTL7)
109
AXI Bus Response Error Interrupt Control Register 0 (AXIRERRCTL0)
110
AXI Bus Response Error Interrupt Control Register 2 (AXIRERRCTL2)
111
AXI Bus Response Error Status Register 0 (AXIRERRST0)
112
AXI Bus Response Error Status Register 2 (AXIRERRST2)
113
AXI Bus Response Error Clear Register 0 (AXIRERRCLR0)
114
AXI Bus Response Error Clear Register 2 (AXIRERRCLR2)
115
Interrupt Request
116
Clock Pulse Generator
117
Features
117
Input/Output Pins
120
Clock Mode
121
Register Descriptions
123
Frequency Control Register (FRQCR)
123
Changing the Frequency
125
Changing the Division Ratio
125
Usage of the Clock Pins
126
In the Case of Inputting an External Clock
126
In the Case of Using a Crystal Resonator
127
In the Case of Not Using the Clock Pin
127
Oscillation Stabilizing Time
128
Oscillation Stabilizing Time of the On-Chip Crystal Oscillator
128
Oscillation Stabilizing Time of the PLL Circuit
128
Notes on Board Design
129
Note on Using a PLL Oscillation Circuit
129
Definition of Modulation Rate and Frequency in the SSCG Specification
130
Clock Signals
131
Clock Signals for the System and Realtime Clock
131
Audio and USB Clock Signals
132
Video Image Clock Signals
132
Other Clock Signals
133
Internal Clock Signals (1)
134
Internal Clock Signals (2)
135
Usage Note
136
Notes on the SSCG
136
Interrupt Controller
137
Features
137
Input/Output Pins
138
Register Descriptions
139
Interrupt Control Register 0 (ICR0)
149
Interrupt Control Register 1 (ICR1)
150
IRQ Interrupt Request Register (IRQRR)
151
Interrupt Sources
152
NMI Interrupt
152
IRQ Interrupts
152
On-Chip Peripheral Module Interrupts
153
Pin Interrupts
154
Interrupt Ids
155
Operation
172
Initial Settings
172
Flow of Interrupt Operations
174
Data Transfer with Interrupt Request Signals
175
Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating
175
Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt
175
Usage Note
176
Timing to Clear Interrupt Source
176
Notes on Selecting IRQ Interrupt Pin Functions
176
Notes on Reading Interrupt ID Values from Interrupt Acknowledge Register (ICCIAR)
176
Notes on Using IRQ Pins as Triggers for Release from Standby When Software Standby Is in Use
177
Bus State Controller
178
Features
178
Input/Output Pins
180
Area Overview
181
Address Map
181
Data Bus Width and Related Pin Setting for each Area Depending on Boot Mode
182
Register Descriptions
183
Common Control Register (CMNCR)
184
Csn Space Bus Control Register (Csnbcr) (N = 0 to 5)
185
Csn Space Wait Control Register (Csnwcr) (N = 0 to 5)
187
SDRAM Control Register (SDCR)
204
Refresh Timer Control/Status Register (RTCSR)
206
Refresh Timer Counter (RTCNT)
207
Refresh Time Constant Register (RTCOR)
207
Timeout Cycle Constant Register (Toscorn) (N = 0 to 5)
208
Timeout Status Register (TOSTR)
209
Timeout Enable Register (TOENR)
211
Operation
212
Access Size and Data Alignment
212
Normal Space Interface
214
Access Wait Control
219
Csn Assert Period Expansion
221
MPX-I/O Interface
222
SDRAM Interface
225
Burst ROM (Clocked Asynchronous) Interface
254
SRAM Interface with Byte Selection
255
Burst ROM (Clocked Synchronous) Interface
260
Wait between Access Cycles
261
Others
264
Direct Memory Access Controller
265
Features
265
Input/Output Pins
266
Register Configuration
266
Register Descriptions
268
Next Source Address Register N (N0Sa_N, N1Sa_N)
276
Next Destination Address Register N (N0Da_N, N1Da_N)
276
Next Transaction Byte Register N (N0Tb_N, N1Tb_N)
277
Current Source Address Register (Crsa_N)
277
Current Destination Address Register (Crda_N)
278
Current Transaction Byte Register (Crtb_N)
278
Channel Status Register N (Chstat_N)
279
Channel Control Register N (Chctrl_N)
282
Channel Configuration Register N (Chcfg_N)
284
Channel Interval Register N (Chitvl_N)
286
Channel Extension Register N (Chext_N)
287
Next Link Address Register N (Nxla_N)
288
Current Link Address Register N (Crla_N)
288
DMA Control Register (DCTRL_0_7, DCTRL_8_15)
289
DMA Status en Register (DSTAT_EN_0_7)
290
DMA Status en Register (DSTAT_EN_8_15)
290
DMA Status er Register (DSTAT_ER_0_7)
291
DMA Status er Register (DSTAT_ER_8_15)
291
DMA Status END Register (DSTAT_END_0_7)
292
DMA Status END Register (DSTAT_END_8_15)
292
DMA Status TC Register (DSTAT_TC_0_7)
293
DMA Status TC Register (DSTAT_TC_8_15)
293
DMA Status SUS Register (DSTAT_SUS_0_7)
294
DMA Status SUS Register (DSTAT_SUS_8_15)
294
DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7)
295
Operation
298
Transfer Flow
298
DMA Transfer Requests
298
DMA Mode
303
Mode Setting
303
Register Mode
303
Link Mode
309
DMA Transfer
316
Transfer Mode
316
Priority Control for DMA Channels
317
Number of States of an External Bus Cycle
319
DMA Transfer Request
319
DMA Acknowledge Output Function
321
DMA Transfer End Output Function
323
DMA Transfer End Interrupt
323
DMA Error Interrupt
324
Interval Count Function
324
Difference in Operation Due to the Transfer Size
325
Transfer Status
326
DMA Setting Examples
330
Setting Example 1 (Register Mode/Hardware Request)
330
Setting Example 2 (Register Mode/Software Request)
332
Setting Example 3 (Register Mode/Continuous Execution)
334
Setting Example 4 (Link Mode)
335
Next Register Set Continuous Execution Setting
338
Note
340
Divided Output of DACK0 and TEND0
340
TEND0 Not Output
341
Atomic Access (ARLOCK[1:0] and AWLOCK[1:0])
341
Multi-Function Timer Pulse Unit 2
342
Features
342
Input/Output Pins
346
Register Descriptions
347
Timer Control Register (TCR)
349
Timer Mode Register (TMDR)
352
Timer I/O Control Register (TIOR)
354
Timer Interrupt Enable Register (TIER)
372
Timer Status Register (TSR)
374
Timer Buffer Operation Transfer Mode Register (TBTM)
377
Timer Input Capture Control Register (TICCR)
378
Timer A/D Converter Start Request Control Register (TADCR)
379
Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4)
381
Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4)
381
Timer Counter (TCNT)
381
Timer General Register (TGR)
382
Timer Start Register (TSTR)
383
Timer Synchronous Register (TSYR)
384
Timer Read/Write Enable Register (TRWER)
385
Timer Output Master Enable Register (TOER)
386
Timer Output Control Register 1 (TOCR1)
387
Timer Output Control Register 2 (TOCR2)
389
Timer Output Level Buffer Register (TOLBR)
392
Timer Gate Control Register (TGCR)
393
Timer Subcounter (TCNTS)
394
Timer Dead Time Data Register (TDDR)
394
Timer Cycle Data Register (TCDR)
395
Timer Cycle Buffer Register (TCBR)
395
Timer Interrupt Skipping Set Register (TITCR)
396
Timer Interrupt Skipping Counter (TITCNT)
398
Timer Buffer Transfer Set Register (TBTER)
399
Timer Dead Time Enable Register (TDER)
400
Timer Waveform Control Register (TWCR)
401
Bus Master Interface
401
Operation
402
Basic Functions
402
Synchronous Operation
408
Buffer Operation
410
Cascaded Operation
414
PWM Modes
419
Phase Counting Mode
423
Reset-Synchronized PWM Mode
429
Complementary PWM Mode
432
A/D Converter Start Request Delaying Function
467
TCNT Capture at Crest And/Or Trough in Complementary PWM Operation
470
Interrupt Sources
471
Interrupt Sources and Priorities
471
Activation of Direct Memory Access Controller
472
A/D Converter Activation
472
Operation Timing
474
Input/Output Timing
474
Interrupt Signal Timing
479
Usage Notes
482
Module Standby Mode Setting
482
Input Clock Restrictions
482
Caution on Period Setting
483
Contention between TCNT Write and Clear Operations
483
Contention between TCNT Write and Increment Operations
484
Contention between TGR Write and Compare Match
484
Contention between Buffer Register Write and Compare Match
485
Contention between Buffer Register Write and TCNT Clear
486
Contention between TGR Read and Input Capture
486
Contention between TGR Write and Input Capture
487
Contention between Buffer Register Write and Input Capture
487
TCNT_2 Write and Overflow/Underflow Contention in Cascade Connection
488
Counter Value During Complementary PWM Mode Stop
489
Buffer Operation Setting in Complementary PWM Mode
489
Reset Sync PWM Mode Buffer Operation and Compare Match Flag
490
Overflow Flags in Reset Synchronous PWM Mode
491
Contention between Overflow/Underflow and Counter Clearing
491
Contention between TCNT Write and Overflow/Underflow
492
Cautions on Transition from Normal Operation or PWM Mode 1
492
To Reset-Synchronized PWM Mode
492
Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode
492
Interrupts in Module Standby Mode
492
Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection
493
Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode
493
Output Pin Initialization for Multi-Function Timer Pulse Unit 2
495
Operating Modes
495
Reset Start Operation
495
Operation in Case of Re-Setting Due to Error During Operation, Etc
496
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation, Etc
497
OS Timer
527
Functional Overview
527
Features of OSTM
527
Registers
528
Registers Overview
528
Details of OSTM Registers
529
Functional Description
533
Block Diagram
533
Count Clock
534
Generation of Interrupt Request
534
Starting and Stopping the Timer
535
Interval Timer Mode
535
Free-Running Comparison Mode
539
Watchdog Timer
542
Features
542
Input/Output Pin
543
Register Descriptions
543
Watchdog Timer Counter (WTCNT)
544
Watchdog Timer Control/Status Register (WTCSR)
544
Watchdog Reset Control/Status Register (WRCSR)
546
Notes on Register Access
547
Usage
549
Canceling Software Standby Mode
549
Using Watchdog Timer Mode
549
Using Interval Timer Mode
550
Usage Notes
551
Timer Variation
551
Prohibition against Setting H'FF to WTCNT
551
Interval Timer Overflow Flag
551
System Reset by WDTOVF Signal
551
Internal Reset in Watchdog Timer Mode
551
Realtime Clock
552
Features
552
Input/Output Pin
554
Register Descriptions
554
64-Hz Counter (R64CNT)
555
Second Counter (RSECCNT)
556
Minute Counter (RMINCNT)
556
Hour Counter (RHRCNT)
557
Day of Week Counter (RWKCNT)
557
Day Counter (RDAYCNT)
558
Month Counter (RMONCNT)
558
Year Counter (RYRCNT)
559
Second Alarm Register (RSECAR)
559
Minute Alarm Register (RMINAR)
560
Hour Alarm Register (RHRAR)
560
Day of Week Alarm Register (RWKAR)
561
Day Alarm Register (RDAYAR)
561
Month Alarm Register (RMONAR)
562
Year Alarm Register (RYRAR)
562
Control Register 1 (RCR1)
563
Control Register 2 (RCR2)
564
Control Register 3 (RCR3)
565
Control Register 5 (RCR5)
565
Frequency Register H/L (RFRH/L)
566
Operation
567
Initial Settings of Registers after Power-On and Oscillation Stabilization Time
567
Setting Time
567
Reading Time
568
Alarm Function
569
Usage Notes
570
Register Writing During Count Operation
570
Use of Realtime Clock Periodic Interrupts
570
Transition to Standby Mode after Setting Register
570
Usage Notes When Writing to and Reading the Register
570
Serial Communication Interface with FIFO
571
Features
571
Input/Output Pins
573
Register Descriptions
574
Receive Shift Register (SCRSR)
575
Receive FIFO Data Register (SCFRDR)
575
Transmit Shift Register (SCTSR)
576
Transmit FIFO Data Register (SCFTDR)
576
Serial Mode Register (SCSMR)
577
Serial Control Register (SCSCR)
579
Serial Status Register (SCFSR)
581
Bit Rate Register (SCBRR)
585
FIFO Control Register (SCFCR)
589
FIFO Data Count Set Register (SCFDR)
591
Serial Port Register (SCSPTR)
592
Line Status Register (SCLSR)
594
Serial Extension Mode Register (SCEMR)
595
Operation
596
Overview
596
Operation in Asynchronous Mode
598
Operation in Clock Synchronous Mode
609
Interrupts
617
Usage Notes
618
SCFTDR Writing and TDFE Flag
618
SCFRDR Reading and RDF Flag
618
Restriction on Direct Memory Controller Usage
618
Break Detection and Processing
618
Sending a Break Signal
619
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
619
Selection of Base Clock in Asynchronous Mode
620
Serial Communications Interface
621
Overview
621
Register Descriptions
623
Receive Shift Register (RSR)
624
Receive Data Register (RDR)
624
Transmit Data Register (TDR)
624
Transmit Shift Register (TSR)
624
Serial Mode Register (SMR)
625
Serial Control Register (SCR)
628
Serial Status Register (SSR)
632
Smart Card Mode Register (SCMR)
636
Bit Rate Register (BRR)
637
Serial Extended Mode Register (SEMR)
641
Noise Filter Setting Register (SNFR)
641
Extended Function Control Register (SECR)
642
Operation in Asynchronous Mode
643
Serial Data Transfer Format
643
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
645
Clock
646
CTS and RTS Functions
646
SCI Initialization (Asynchronous Mode)
647
Serial Data Transmission (Asynchronous Mode)
648
Serial Data Reception (Asynchronous Mode)
650
Multi-Processor Communications Function
654
Multi-Processor Serial Data Transmission
655
Multi-Processor Serial Data Reception
656
Operation in Clock Synchronous Mode
659
Clock
659
CTS and RTS Functions
659
Initialization (Clock Synchronous Mode)
660
Serial Data Transmission (Clock Synchronous Mode)
661
Serial Data Reception (Clock Synchronous Mode)
663
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
666
Operation in Smart Card Interface Mode
667
Sample Connection
667
Data Format (Except in Block Transfer Mode)
668
Block Transfer Mode
670
Receive Data Sampling Timing and Reception Margin
670
Initialization (Smart Card Interface Mode)
671
Serial Data Transmission (Except in Block Transfer Mode)
672
Serial Data Reception (Except in Block Transfer Mode)
675
Clock Output Control
676
Noise Cancellation Function
678
Interrupt Sources
679
Interrupts in Serial Communications Interface Mode
679
Interrupts in Smart Card Interface Mode
680
Usage Notes
681
Setting the Module Standby Function
681
Break Detection and Processing
681
The Mark State and Production of Breaks
681
Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
681
Writing Data to TDR
681
Restrictions on Clock Synchronous Transmission
681
Restrictions on Using DMAC
681
Points to Note on Starting Transfer
681
SCI Operations During Low Power Consumption State
682
External Clock Input in Clock Synchronous Mode
684
15.10 Irda Communications
685
15.11 Irda Register Description
686
Irda Control Register (IRCR)
686
15.12 Irda Operation
687
Flow of Irda Setting
687
Transmission
687
Reception
688
Selection of High-Level Pulse Width
688
15.13 Notes on Using the Irda Module
689
Shortest Pulse Width in Reception
689
Asynchronous Basic Clock for Serial Communication Interface
689
Renesas Serial Peripheral Interface
690
Features
690
Input/Output Pins
692
Register Descriptions
693
Control Register (SPCR)
695
Slave Select Polarity Register (SSLP)
696
Pin Control Register (SPPCR)
696
Status Register (SPSR)
697
Data Register (SPDR)
699
Sequence Control Register (SPSCR)
699
Sequence Status Register (SPSSR)
700
Bit Rate Register (SPBR)
700
Data Control Register (SPDCR)
701
Clock Delay Register (SPCKD)
702
Slave Select Negation Delay Register (SSLND)
703
Next-Access Delay Register (SPND)
704
Command Register (SPCMD)
705
Buffer Control Register (SPBFCR)
707
Buffer Data Count Setting Register (SPBFDR)
708
Operation
709
Overview of Operations
709
Pin Control
710
System Configuration Example
710
Transfer Format
713
Data Format
715
Error Detection
721
Initialization
723
SPI Operation
724
Error Handling
734
Loopback Mode
735
Interrupt Sources
735
SPI Multi I/O Bus Controller
736
Features
736
Block Diagram
737
Input/Output Pins
738
Register Descriptions
739
Common Control Register (CMNCR)
740
SSL Delay Register (SSLDR)
743
Bit Rate Register (SPBCR)
744
Data Read Control Register (DRCR)
746
Data Read Command Setting Register (DRCMR)
747
Data Read Extended Address Setting Register (DREAR)
748
Data Read Option Setting Register (DROPR)
749
Data Read Enable Setting Register (DRENR)
750
SPI Mode Control Register (SMCR)
752
SPI Mode Command Setting Register (SMCMR)
753
SPI Mode Address Setting Register (SMADR)
753
SPI Mode Option Setting Register (SMOPR)
754
SPI Mode Enable Setting Register (SMENR)
755
SPI Mode Read Data Register 0 (SMRDR0)
757
SPI Mode Read Data Register 1 (SMRDR1)
757
SPI Mode Write Data Register 0 (SMWDR0)
758
SPI Mode Write Data Register 1 (SMWDR1)
758
Common Status Register (CMNSR)
759
SPI AC Input Characteristics Adjustment Register (CKDLY) (RZ/A1LU Only)
760
Data Read Dummy Cycle Setting Register (DRDMCR)
761
Data Read DDR Enable Register (DRDRENR) (RZ/A1LU Only)
762
SPI Mode Dummy Cycle Setting Register (SMDMCR)
763
SPI Mode DDR Enable Register (SMDRENR) (RZ/A1LU Only)
764
SPI AC Output Characteristics Adjustment Register (SPODLY) (RZ/A1LU Only)
765
Operation
766
System Configuration
766
Address Map
767
32-Bit Serial Flash Addresses
767
Data Alignment
768
Operating Modes
769
External Address Space Read Mode
769
Read Cache
774
SPI Operating Mode
775
Transfer Format
778
Data Format
780
Data Pin Control
785
SPBSSL Pin Control
787
Flags
787
Usage Notes
788
Notes on Transfer to Read Data in SPI Operating Mode
788
Notes on Starting Transfer from the SPBSSL Retained State in SPI Operating Mode
788
I²C Bus Interface
789
Features
789
Channels
789
Register Base Addresses
789
External I/O Signals
790
Overview
791
Functional Overview
791
Block Diagram
793
Registers
795
Riicncr1 - I²C Bus Control Register 1
795
Riicncr2 - I²C Bus Control Register 2
798
Riicnmr1 - I²C Bus Mode Register 1
802
Riicnmr2 - I²C Bus Mode Register 2
804
Riicnmr3 - I²C Bus Mode Register 3
806
Riicnfer - I²C Bus Function Enable Register
809
Riicnser - I²C Bus Status Enable Register
811
Riicnier - I²C Bus Interrupt Enable Register
813
Riicnsr1 - I²C Bus Status Register 1
815
Riicnsr2 - I²C Bus Status Register 2
818
Riicnsary - I²C Slave Address Register y (y = 0 to 2)
823
Riicnbrl - I²C Bus Bit Rate Low-Level Register
825
Riicnbrh - I²C Bus Bit Rate High-Level Register
826
Riicndrt - I²C Bus Transmit Data Register
829
Riicndrr - I²C Bus Receive Data Register
830
Riicndrs - I²C Bus Shift Register
831
Interrupt Sources
832
Operation
833
Communication Data Format
833
Initial Settings
834
Master Transmit Operation
835
Master Receive Operation
840
Slave Transmit Operation
846
Slave Receive Operation
849
SCL Synchronization Circuit
852
Facility for Delaying SDA Output
853
Digital Noise-Filter Circuits
854
Address Match Detection
855
Slave-Address Match Detection
855
Detection of the General Call Address
857
Device-ID Address Detection
858
Host Address Detection
860
18.10 Automatically Low-Hold Function for SCL
861
Function to Prevent Wrong Transmission of Transmit Data
861
NACK Reception Transfer Suspension Function
862
Function to Prevent Failure to Receive Data
863
18.11 Arbitration-Lost Detection Functions
865
Master Arbitration-Lost Detection (MALE Bit)
865
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
867
Slave Arbitration-Lost Detection (SALE Bit)
868
18.12 Start Condition/Restart Condition/Stop Condition Issuing Function
869
Issuing a Start Condition
869
Issuing a Restart Condition
869
Issuing a Stop Condition
871
18.13 Bus Hanging
872
Timeout Function
872
Extra SCL Clock Cycle Output Function
874
RIIC Reset and Internal Reset
875
18.14 Smbus Operation
876
Smbus Timeout Measurement
876
Smbus Host Notification Protocol/Notify ARP Master
877
18.15 Reset Function of RIIC
878
Serial Sound Interface
880
Features
880
Input/Output Pins
882
Register Description
883
Control Register (SSICR)
885
Status Register (SSISR)
889
Transmit Data Register (SSITDR)
891
Receive Data Register (SSIRDR)
891
FIFO Control Register (SSIFCR)
892
FIFO Status Register (SSIFSR)
894
Transmit FIFO Data Register (SSIFTDR)
896
Receive FIFO Data Register (SSIFRDR)
896
TDM Mode Register (SSITDMR)
897
FC Control Register (SSIFCCR)
898
FC Mode Register (SSIFCMR)
899
FC Status Register (SSIFCSR)
900
Operation Description
901
Bus Format
901
Non-Compressed Modes
902
TDM Mode
910
WS Continue Mode
911
Operation Modes
911
Transmit Operation
912
Receive Operation
915
Serial Bit Clock Control
917
Usage Notes
918
Limitations from Underflow or Overflow During DMA Operation
918
Note on Changing Mode from Master Transceiver to Master Receiver
918
Limits on TDM Mode and WS Continue Mode
918
Media Local Bus
919
Features
919
Input/Output Pins
920
Register Description
920
CAN Interface
921
Overview
921
Units
921
Register Addresses
922
Clock Supply
922
Interrupts
923
I/O Signals
923
Function
924
Block Diagram
926
Registers
927
Rscan0Cmcfg - Channel Configuration Register (M = 0 or 1)
940
Rscan0Cmctr - Channel Control Register (M = 0 or 1)
942
Rscan0Cmsts - Channel Status Register (M = 0 or 1)
946
Rscan0Cmerfl - Channel Error Flag Register (M = 0 or 1)
948
RSCAN0GCFG - Global Configuration Register
952
RSCAN0GCTR - Global Control Register
955
RSCAN0GSTS - Global Status Register
957
RSCAN0GERFL - Global Error Flag Register
959
RSCAN0GTINTSTS0 - Global TX Interrupt Status Register 0
960
RSCAN0GTSC - Global Timestamp Counter Register
962
RSCAN0GAFLECTR - Receive Rule Entry Control Register
963
RSCAN0GAFLCFG0 - Receive Rule Configuration Register 0
964
Rscan0Gaflidj - Receive Rule ID Register (J = 0 to 15)
965
Rscan0Gaflmj - Receive Rule Mask Register (J = 0 to 15)
967
Rscan0Gaflp0J - Receive Rule Pointer 0 Register (J = 0 to 15)
968
Rscan0Gaflp1J - Receive Rule Pointer 1 Register (J = 0 to 15)
970
RSCAN0RMNB - Receive Buffer Number Register
971
Rscan0Rmndy - Receive Buffer New Data Register y (y = 0)
972
Rscan0Rmidq - Receive Buffer ID Register (Q = 0 to 31)
973
Rscan0Rmptrq - Receive Buffer Pointer Register (Q = 0 to 31)
974
Rscan0Rmdf0Q - Receive Buffer Data Field 0 Register (Q = 0 to 31)
975
Rscan0Rmdf1Q - Receive Buffer Data Field 1 Register (Q = 0 to 31)
976
Rscan0Rfccx - Receive FIFO Buffer Configuration and Control Register (X = 0 to 7)
977
Rscan0Rfstsx - Receive FIFO Buffer Status Register (X = 0 to 7)
979
Rscan0Rfpctrx - Receive FIFO Buffer Pointer Control Register (X = 0 to 7)
981
Rscan0Rfidx - Receive FIFO Buffer Access ID Register (X = 0 to 7)
982
Rscan0Rfptrx - Receive FIFO Buffer Access Pointer Register (X = 0 to 7)
983
Rscan0Rfdf0X - Receive FIFO Buffer Access Data Field 0 Register (X = 0 to 7)
984
Rscan0Rfdf1X - Receive FIFO Buffer Access Data Field 1 Register (X = 0 to 7)
985
Rscan0Cfcck - Transmit/Receive FIFO Buffer Configuration and Control Register K (K = 0 to 5)
986
Rscan0Cfstsk - Transmit/Receive FIFO Buffer Status Register (K = 0 to 5)
990
Rscan0Cfpctrk - Transmit/Receive FIFO Buffer Pointer Control Register (K = 0 to 5)
993
Rscan0Cfidk - Transmit/Receive FIFO Buffer Access ID Register (K = 0 to 5)
995
Rscan0Cfptrk - Transmit/Receive FIFO Buffer Access Pointer Register (K = 0 to 5)
997
Rscan0Cfdf0K - Transmit/Receive FIFO Buffer Access Data Field 0 Register (K = 0 to 5)
999
Rscan0Cfdf1K - Transmit/Receive FIFO Buffer Access Data Field 1 Register (K = 0 to 5)
1000
RSCAN0FESTS - FIFO Empty Status Register
1001
RSCAN0FFSTS - FIFO Full Status Register
1002
RSCAN0FMSTS - FIFO Message Lost Status Register
1003
RSCAN0RFISTS - Receive FIFO Buffer Interrupt Flag Status Register
1004
RSCAN0CFRISTS - Transmit/Receive FIFO Buffer Receive Interrupt Flag Status Register
1005
RSCAN0CFTISTS - Transmit/Receive FIFO Buffer Transmit Interrupt Flag Status Register
1006
Rscan0Tmcp - Transmit Buffer Control Register (P = 0 to 31)
1007
Rscan0Tmstsp - Transmit Buffer Status Register (P = 0 to 31)
1009
Rscan0Tmtrstsy - Transmit Buffer Transmit Request Status Register y (y = 0)
1011
Rscan0Tmtarstsy - Transmit Buffer Transmit Abort Request Status Register y (y = 0)
1012
Rscan0Tmtcstsy - Transmit Buffer Transmit Complete Status Register y (y = 0)
1013
Rscan0Tmtastsy - Transmit Buffer Transmit Abort Status Register y (y = 0)
1014
Rscan0Tmiecy - Transmit Buffer Interrupt Enable Configuration Register y (y = 0)
1015
Rscan0Tmidp - Transmit Buffer ID Register (P = 0 to 31)
1016
Rscan0Tmptrp - Transmit Buffer Pointer Register (P= 0 to 31)
1017
Rscan0Tmdf0P - Transmit Buffer Data Field 0 Register (P = 0 to 31)
1018
Rscan0Tmdf1P - Transmit Buffer Data Field 1 Register (P = 0 to 31)
1019
Rscan0Txqccm - Transmit Queue Configuration and Control Register (M = 0 or 1)
1020
Rscan0Txqstsm - Transmit Queue Status Register (M = 0 or 1)
1022
Rscan0Txqpctrm - Transmit Queue Pointer Control Register (M = 0 or 1)
1024
Rscan0Thlccm - Transmit History Configuration and Control Register (M = 0 or 1)
1025
Rscan0Thlstsm - Transmit History Status Register (M = 0 or 1)
1027
Rscan0Thlaccm - Transmit History Access Register (M = 0 or 1)
1029
Rscan0Thlpctrm - Transmit History Pointer Control Register (M = 0 or 1)
1030
RSCAN0GTSTCFG - Global Test Configuration Register
1031
RSCAN0GTSTCTR - Global Test Control Register
1032
RSCAN0GLOCKK - Global Lock Key Register
1033
Interrupt Sources
1034
RSCAN Modes
1038
Global Modes
1038
Channel Modes
1041
Reception Function
1046
Data Processing Using the Receive Rule Table
1046
Transmission Functions
1050
Transmit Priority Determination
1051
Transmission Using Transmit Buffers
1051
Transmission Using FIFO Buffers
1052
Transmission Using Transmit Queues
1055
Transmit History Function
1055
Gateway Function
1057
Test Function
1058
Standard Test Mode
1058
Listen-Only Mode
1058
Self-Test Mode (Loopback Mode)
1059
Inter-Channel Communication Test
1061
21.10 RS-CAN Setting Procedure
1062
Initial Settings
1062
Reception Procedure
1068
Transmission Procedure
1073
Test Settings
1082
21.11 Notes on the RS-CAN Module
1084
Iebus Controller
1085
IEBB Features
1085
Configuration
1087
Function Overview
1087
Block Diagram
1088
Registers
1089
Iebbn Register Overview
1089
Iebbn Control Register Details
1090
Interrupt Operations
1156
Interrupt Request Signals
1156
Interrupt Judgment Examples
1161
Operation
1163
Fifo
1163
Initial Settings
1165
Master Transmission (Single Mode)
1166
Master Transmission (FIFO Mode)
1168
Master Reception (Single Mode)
1170
Master Reception (FIFO Mode)
1172
Slave Transmission (Single Mode)
1174
Slave Transmission (FIFO Mode)
1177
Slave Reception (Single Mode)
1180
Slave Reception (FIFO Mode)
1182
Setup Procedures
1183
Master Transmission (Single Mode)
1183
Master Transmission (FIFO Mode)
1184
Master Reception (Single Mode)
1185
Master Reception (FIFO Mode)
1186
Slave Transmission (Single Mode)
1187
Slave Transmission (FIFO Mode)
1190
Slave Reception (Single Mode)
1193
Slave Reception (FIFO Mode)
1194
Functions
1195
Iebus Communication Protocol
1195
Determination of Bus Mastership (Arbitration)
1196
Communication Mode
1196
Communication Address
1197
Broadcast Communication
1197
Iebus Transfer Format
1198
Transfer Data
1208
Bit Format
1212
Renesas SPDIF Interface
1213
Overview
1213
Features
1213
Functional Block Diagram
1214
Input/Output Pins
1215
Renesas SPDIF (IEC60958) Frame Format
1215
Register
1217
Register Descriptions
1218
Control Register (CTRL)
1218
Status Register (STAT)
1221
Transmitter Channel 1 Audio Register (TLCA)
1223
Transmitter Channel 2 Audio Register (TRCA)
1224
Transmitter DMA Audio Data Register (TDAD)
1224
Transmitter User Data Register (TUI)
1225
Transmitter Channel 1 Status Register (TLCS)
1226
Transmitter Channel 2 Status Register (TRCS)
1227
Receiver Channel 1 Audio Register (RLCA)
1228
Receiver Channel 2 Audio Register (RRCA)
1228
Receiver DMA Audio Data (RDAD)
1229
Receiver User Data Register (RUI)
1230
Receiver Channel 1 Status Register (RLCS)
1231
Receiver Channel 2 Status Register (RRCS)
1232
Functional Description-Transmitter
1233
Transmitter Module
1233
Transmitter Module Initialization
1233
Initial Settings for Transmitter Module
1234
Transmitter Module Data Transfer
1234
Functional Description-Receiver
1236
Receiver Module
1236
Receiver Module Initialization
1236
Receiver Module Data Transfer
1237
23.10 Disabling the Module
1239
Transmitter and Receiver Idle
1239
23.11 Compressed Mode Data
1239
23.12 References
1239
23.13 Usage Notes
1240
Clearing TUIR
1240
Frequency of Clock Input for Audio
1240
CD-ROM Decoder
1241
Features
1241
Formats Supported by CD-ROM Decoder
1242
Block Diagrams
1242
Register Descriptions
1245
Enable Control Register (CROMEN)
1247
Sync Code-Based Synchronization Control Register (CROMSY0)
1248
Decoding Mode Control Register (CROMCTL0)
1249
EDC/ECC Check Control Register (CROMCTL1)
1250
Automatic Decoding Stop Control Register (CROMCTL3)
1251
Decoding Option Setting Control Register (CROMCTL4)
1252
HEAD20 to HEAD22 Representation Control Register (CROMCTL5)
1253
Sync Code Status Register (CROMST0)
1253
Post-ECC Header Error Status Register (CROMST1)
1254
Post-ECC Subheader Error Status Register (CROMST3)
1254
Header/Subheader Validity Check Status Register (CROMST4)
1255
Mode Determination and Link Sector Detection Status Register (CROMST5)
1256
ECC/EDC Error Status Register (CROMST6)
1257
Buffer Status Register (CBUFST0)
1257
Decoding Stoppage Source Status Register (CBUFST1)
1258
Buffer Overflow Status Register (CBUFST2)
1258
Pre-ECC Correction Header: Minutes Data Register (HEAD00)
1259
Pre-ECC Correction Header: Seconds Data Register (HEAD01)
1259
Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02)
1259
Pre-ECC Correction Header: Mode Data Register (HEAD03)
1259
Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00)
1260
Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01)
1260
Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02)
1260
Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03)
1261
Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04)
1261
Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05)
1261
Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06)
1262
Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07)
1262
Post-ECC Correction Header: Minutes Data Register (HEAD20)
1262
Post-ECC Correction Header: Seconds Data Register (HEAD21)
1263
Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22)
1263
Post-ECC Correction Header: Mode Data Register (HEAD23)
1263
Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20)
1264
Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21)
1264
Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22)
1264
Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23)
1265
Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24)
1265
Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25)
1265
Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26)
1266
Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27)
1266
Automatic Buffering Setting Control Register (CBUFCTL0)
1267
Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1)
1268
Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2)
1268
Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3)
1268
ISY Interrupt Source Mask Control Register (CROMST0M)
1269
CD-ROM Decoder Reset Control Register (ROMDECRST)
1269
CD-ROM Decoder Reset Status Register (RSTSTAT)
1270
Serial Sound Interface Data Control Register (SSI)
1271
Interrupt Flag Register (INTHOLD)
1272
Interrupt Source Mask Control Register (INHINT)
1273
CD-ROM Decoder Stream Data Input Register (STRMDIN0)
1273
CD-ROM Decoder Stream Data Input Register (STRMDIN2)
1274
CD-ROM Decoder Stream Data Output Register (STRMDOUT0)
1274
Operation
1275
Endian Conversion for Data in the Input Stream
1275
Sync Code Maintenance Function
1276
Error Correction
1278
Automatic Decoding Stop Function
1279
Buffering Format
1280
Target-Sector Buffering Function
1281
Interrupt Sources
1283
Interrupt and DMA Transfer Request Signals
1283
Timing of Status Registers Updates
1284
Usage Notes
1285
Stopping and Resuming Buffering Alone During Decoding
1285
Setting Sync Code Status Register (CROMST0)
1285
Link Blocks
1285
Stopping and Resuming CD-DSP Operation
1285
Note on Clearing the IREADY Flag
1286
Note on Stream Data Transfer (1)
1286
Note on Stream Data Transfer (2)
1286
Note on Software Reset
1286
LIN Interface
1287
Features
1287
Channels
1287
Register Addresses
1287

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Renesas RZ/A1LU Manuallines

Renesas RZ/A1LU Manuallines (19 pages)

High-Speed USB2.0 Board Design

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