Notes On Register Access - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
12.3.4

Notes on Register Access

The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and watchdog reset control/
status register (WRCSR) are more difficult to write to than other registers. The procedures for reading or writing to these
registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written by a 16-bit transfer instruction. They cannot be written by an 8- or 32-bit transfer
instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in Figure
12.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer
procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
Address: H'FCFE0002
WTCSR write
Address: H'FCFE0000
Figure 12.2 Writing to WTCNT and WTCSR
(2) Writing to WRCSR
WRCSR must be written by a 16-bit access to address H'FCFE0004. It cannot be written by 8- or 32-bit transfer
instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) are different, as shown in Figure 12.3.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the
WOVF bit to 0. The RSTE bit is not affected. To write to the RSTE bit, the upper byte must be H'5A and the lower byte
must be the write data. The value of bit 6 of the lower byte is transferred to the RSTE bit. The WOVF bit is not affected.
Writing 0 to the WOVF bit
Address: H'FCFE0004
Writing to the RSTE bit
Address: H'FCFE0004
Figure 12.3 Writing to WRCSR
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
15
H'5A
15
H'A5
15
H'A5
15
H'5A
8 7
Write data
8 7
Write data
8 7
H'00
8 7
Write data
12. Watchdog Timer
0
0
0
0
12-6