Data Pin Control - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.11

Data Pin Control

With this module, the status of pins can be automatically changed based on the data size to be used and the read/write
settings. The pin status during the SPBSSL negation can be set with the MOIIO3, MOIIO2, MOIIO1, and MOIIO0 bits
in CMNCR. The SPBSSL and SPBCLK pins are always output pins. The status of respective pins is specified in Table
17.6 to Table 17.9.
Table 17.6 Pin Status (1)
Pin SPBSSL Negation
SPBMO0/ MOIIO0 bit value
SPBIO00,
SPBMO1/
SPBIO01
SPBMI0/ MOIIO1 bit value
SPBIO10,
SPBMI1/
SPBIO11
SPBIO20, SPBIO21 MOIIO2 bit value
SPBIO30, SPBIO31 MOIIO3 bit value
Table 17.7 Pin Status (2)
Pin 1-bit Size
SPBMO0/ IO0FV bit value
SPBIO00,
SPBMO1/
SPBIO01
SPBMI0/ Input
SPBIO10,
SPBMI1/
SPBIO11
SPBIO20, SPBIO21 IO2FV bit value
SPBIO30, SPBIO31 IO3FV bit value
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
1-bit Size
Output
Hi-Z
IO2FV bit value
IO3FV bit value
External Address Space Read Operation
2-bit Size
Input
Input
IO2FV bit value
IO3FV bit value
SPBSSL Assertion
Command, Optional Command, Address, Option Data
2-bit Size
Output
Output
IO2FV bit value
IO3FV bit value
Transfer Data
4-bit Size 1-bit Size
Input IO0FV bit value
Input Input
Input IO2FV bit value
Input IO3FV bit value
17. SPI Multi I/O Bus Controller
4-bit Size
Output
Output
Output
Output
SPI Operation
SPIRE Bit = 1, SPIWE Bit = 0
2-bit Size 4-bit Size
Input Input
Input Input
IO2FV bit value Input
IO3FV bit value Input
17-50