Usage Notes; Limitations From Underflow Or Overflow During Dma Operation; Note On Changing Mode From Master Transceiver To Master Receiver; Limits On Tdm Mode And Ws Continue Mode - Renesas RZ/A Series User Manual

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Table of Contents

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Usage Notes

If an underflow or overflow occurs while the DMA is in operation, the module should be restarted. The transmit and

receive buffers in the SSIF consists of 32-bit registers that share the L and R channels. Therefore, data to be transmitted

and received at the L channel may sometimes be transmitted and received at the R channel if an underflow or overflow

occurs, for example, under the following condition: the control register (SSICR) has a 32-bit setting for both data word

length (DWL2 to DWL0) and system word length (SWL2 to SWL0).

If an error interrupt (transmit underflow, transmit overflow, receive underflow, and receive overflow) or setting of a

corresponding error status flag (the bits TUIRQ, TOIRQ, RUIRQ, and ROIRQ in SSISR) indicates an error, write 0 to

the TEN or REN bit in SSICR to disable DMA transfer requests from this module, thus stopping the operation. Make the

setting to stop the direct memory access controller. After this, if reception had been in progress, write 0 to the error status

flag bit to clear it, set the direct memory access controller again, and restart the transfer. For transmission, issue a

software reset and execute the procedure to start again.

If a transmit underflow occurs in master transceiver mode while WS continue mode is disabled (SSITDMR.CONT = 0)

and the TEN bit in SSICR is set to 0 in order to disable transmit operation, SSIWS output is broken. In order to receive

seamlessly after changing mode to master receiver mode, write dummy data to SSIFTDR to suppress transmit underflow.

If TDM mode or WS continue mode setting is changed, the operation of the SSISCK and SSIWS signals immediately

after switching are not guaranteed. If it affects the device to be connected, do not change the setting dynamically.

To temporarily halt and restart transmission while the WS continue mode is enabled (SSITDMR.CONT = 1), after

writing to the transmit FIFO data register (SSIFTDR) a multiple of two times, use the transmit underflow error interrupt

or the corresponding error status flag (SSISR.TUIRQ) to confirm that an error has occurred, and then write 0 to the TEN

bit of the SSISCR register.

Note that after the transmit underflow error, the last value written to SSIFTDR will be repeatedly sent as long as

SSISCR.TEN = 1. Therefore, write a dummy value as the last data for transmission or mute the signal by writing 1 to the

MUEN bit of the SSISCR register.

To restart transmission, do not apply a software reset; after writing 0 to the error status flag bit to clear it, use the idle

mode status flag (SSISR.IDST) to confirm that this module is in the idle state, and then write 1 to the TEN bit of the

SSISCR register.

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

19. Serial Sound Interface

Rz/a1 series Rz/a1lu series Rz/a1lc series