Rscan0Cfcck - Transmit/Receive Fifo Buffer Configuration And Control Register K (K = 0 To 5) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.30 RSCAN0CFCCk — Transmit/receive FIFO buffer Configuration and Control
Register k (k = 0 to 5)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0118
Initial value: 0000 0000
Bit 31 30 29
Initial value 0 0 0
R/W R/W R/W R/W
Bit 15 14 13
CFIGCV[2:0]
0 0 0
Initial value
R/W R/W R/W R/W
Table 21.44
Bit Position
31 to 24
23 to 20
19
18
17, 16
15 to 13
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (k * 0004 )
H H
H
28 27 26
CFITT[7:0]
0 0 0
R/W R/W R/W
12 11 10
CFIM — CFDC[2:0]
0 0 0
R/W R R/W
RSCAN0CFCCk register contents (1/2)
Bit Name Function
CFITT[7:0] Set a message transmission interval.
Set Value: 00
CFTML[3:0] Transmit Buffer Link Configuration
Set the transmit buffer number to be linked to the transmit/receive FIFO buffer.
CFITR Transmit/Receive FIFO Interval Timer Resolution
CFITSS Transmit/Receive FIFO Interval Timer Clock Source Select
CFM[1:0] Transmit/Receive FIFO Mode Select
b17 b16
CFIGCV[2:0] Transmit/Receive FIFO Receive Interrupt Request Timing Select
b15 b14 b13
25 24 23 22
CFTML[3:0]
0 0 0 0
R/W R/W R/W R/W
9 8 7 6
— —
0 0 0 0
R/W R/W R R
to FF
H H
0: Clock dividing pclk by ((ITRCP [15:0] bits)
1: Clock dividing pclk by ((ITRCP [15:0] bits × 10)
0: Interval timer clock source selected by the CFITR bit
1: Interval timer clock source is the bit time clock for the channel to which the
FIFO is linked.
0 0: Receive mode
0 1: Transmit mode
1 0: Gateway mode
1 1: Setting prohibited
0 0 0: When FIFO is 1/8 full.
0 0 1: When FIFO is 2/8 full.
0 1 0: When FIFO is 3/8 full.
0 1 1: When FIFO is 4/8 full.
1 0 0: When FIFO is 5/8 full.
1 0 1: When FIFO is 6/8 full.
1 1 0: When FIFO is 7/8 full.
1 1 1: When FIFO is full.
21. CAN Interface
21 20 19 18
CFITR CFITSS
0 0 0 0
R/W R/W R/W R/W
5 4 3 2
— — — CFTXIE CFRXIE
0 0 0 0
R R R R/W
17 16
CFM[1:0]
0 0
R/W R/W
1 0
CFE
0 0
R/W R/W
21-66