Riicncr2 - I²C Bus Control Register 2 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.2 RIICnCR2 — I²C Bus Control Register 2
Access: RIICnCR2 is a 32-bit readable/writable register.
RIICnCR2L and RIICnCR2H are 16-bit readable/writable registers.
RIICnCR2LL, RIICnCR2LH, RIICnCR2HL, and RIICnCR2HH are 8-bit readable/writable registers.
Address: RIICnCR2: <RIICn_base> + 0004
RIICnCR2L: <RIICn_base> + 0004
RIICnCR2LL: <RIICn_base> + 0004
RIICnCR2HH: <RIICn_base> + 0007
Initial Value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.7
Bit Position
31 to 8
7
6
5
4
3
2
1
0
ST Bit (Start Condition Issuance Request)
This bit is used to request transition to master mode and issuance of a start condition.
When this bit is set to 1 to request to issue a start condition, a start condition is issued when the BBSY
flag is set to 0 (bus free).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnCR2H: <RIICn_base> + 0006
H
, RIICnCR2LH: <RIICn_base> + 0005
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnCR2 register contents
Bit Name Function
— Reserved
These bits are read as 0. The write value should be 0.
BBSY Bus Busy Detection Flag
0: The I
1: The I
MST Master/Slave Mode
0: Slave mode
1: Transmit mode
TRS Transmit/Receive Mode
0: Receive mode
1: Transmit mode
— Reserved
This bit is read as 0. The write value should be 0.
SP Stop Condition Issuance Request
0: Does not request to issue a stop condition.
1: Requests to issue a stop condition.
RS Restart Condition Issuance Request
0: Does not request to issue a restart condition.
1: Requests to issue a restart condition.
ST Start Condition Issuance Request
0: Does not request to issue a start condition.
1: Requests to issue a start condition.
— Reserved
This bit is read as 0. The write value should be 0.
H
, RIICnCR2HL: <RIICn_base> + 0006
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — BBSY MST
0 0 0 0
R R R R
2
C bus is released (bus free state).
2
C bus is occupied (bus busy state or in the bus free state).
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
TRS — SP RS
0 0 0 0
R R R/W R/W
,
H
17 16
— —
0 0
R R
1 0
ST —
0 0
R/W R
18-10