Ws Continue Mode; Operation Modes - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
19.4.4

WS Continue Mode

In WS continue mode, the SSIWS signal continues to be output irrespective whether data transfer is enabled or disabled.
This mode can be set using the CONT bit in the TDM mode register (SSITDMR). With this mode enabled, the SSIWS
signal does not stop but continues operating even if TEN and REN bits in the control register (SSICR) are both set to 0
(transfer disabled). While transfer is disabled, the SSITxD pin outputs 0 if the MUEN bit in SSICR is set to 0, and
outputs the value specified by the SPDP bit in SSICR if the MUEN bit is set to 0. With this mode disabled, the SSIWS
signal stops if TEN and REN bits are both set to 0.
Figure 19.20 and Figure 19.21 show the operations with WS continue mode enabled and disabled, respectively.
SSISCK
SSIWS
SSIDATA
Figure 19.20 WS Continue Mode Enabled
SSISCK
SSIWS
SSIDATA
Figure 19.21 WS Continue Mode Disabled
19.4.5

Operation Modes

There are three modes of operation: configuration, enabled and disabled. Figure 19.22 shows how the module enters
each of these modes.
Figure 19.22 Operation Modes
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
LSB MSB LSB
LSB MSB LSB
TEN = 0
and
REN = 0
(IDST = 1)
Module disabled
(waiting until
bus inactive)
Data transfer disabled period (TEN = 0, REN = 0)
Data transfer disabled period (TEN = 0, REN = 0)
Reset
Module
configuration
(after reset)
TEN = 1
or
REN = 1
(IDST = 0)
Module enabled
TEN = 0
(normal tx/rx)
and
REN = 0
(IDST = 0)
19. Serial Sound Interface
MSB LSB MSB
MSB LSB MSB
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